diff options
author | gatecat <gatecat@ds0.me> | 2021-04-14 09:42:23 +0100 |
---|---|---|
committer | gatecat <gatecat@ds0.me> | 2021-04-19 19:49:52 +0100 |
commit | a25240d8c39e7260ef71ea8724dc2f4d09b54d08 (patch) | |
tree | 9709b44d954394d0e49f2274adc95c9c52cdfe0d /docs/index.rst | |
parent | 71720ab240136076ea0d22424f1ab88be0ba00f9 (diff) | |
download | fpga-interchange-schema-a25240d8c39e7260ef71ea8724dc2f4d09b54d08.tar.gz fpga-interchange-schema-a25240d8c39e7260ef71ea8724dc2f4d09b54d08.tar.bz2 fpga-interchange-schema-a25240d8c39e7260ef71ea8724dc2f4d09b54d08.zip |
Add specification of default cell pin values
This adds structures for DeviceResources for the default values for cell
pins that are missing or disconnected.
Previously the contract was that the synthesis tool would always give
cell pins a value, but this has several problems:
- existing flows aren't doing this
- cells might want to be created by the PnR tool or anything else
reading the interchange format
- sometimes, floating is a valid default value (for example certain
dedicated pins) and the existing contract didn't recognise that
- setting all disconnected pins to ground is definitely not correct,
vendor tools usually connect disconnected clock enables to Vcc for
example.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'docs/index.rst')
0 files changed, 0 insertions, 0 deletions