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| author | Karol Gugala <kgugala@antmicro.com> | 2021-04-29 15:22:57 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-29 15:22:57 +0200 |
| commit | b3ab09776c8dc31a71ca2c7fbcb4575219232d16 (patch) | |
| tree | 901bb7bd57e6a1883987d7adc408411e8a14cdbc /docs/requirements.txt | |
| parent | 5208d794d318e9151b93120d7e5ba75d8aef45e7 (diff) | |
| parent | 04bc92a22306351e1b848a6d8a3fd7720c4aed58 (diff) | |
| download | fpga-interchange-schema-b3ab09776c8dc31a71ca2c7fbcb4575219232d16.tar.gz fpga-interchange-schema-b3ab09776c8dc31a71ca2c7fbcb4575219232d16.tar.bz2 fpga-interchange-schema-b3ab09776c8dc31a71ca2c7fbcb4575219232d16.zip | |
Merge pull request #31 from gatecat/wire-general-routing
Add Wire types and categories
Diffstat (limited to 'docs/requirements.txt')
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