diff options
| -rw-r--r-- | src/ghdl.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index ef2ddaf..6f7ff3a 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -680,6 +680,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) } break; case Id_Inout: + case Id_Iinout: // The wire was created when the port was. break; case Id_Assert: @@ -983,6 +984,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) module->connect(OUT (0), IN (0)); break; case Id_Inout: + case Id_Iinout: // Virtual gate. // Connect input to output. module->connect(OUT(0), IN(0)); |