diff options
| -rw-r--r-- | src/ghdl.cc | 8 | ||||
| -rwxr-xr-x | testsuite/pr64/testsuite.sh | 10 | ||||
| -rw-r--r-- | testsuite/pr64/vector.vhdl | 16 |
3 files changed, 34 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 1d26ded..91239e5 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -306,6 +306,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Lsr: case Id_Lsl: case Id_Asr: + case Id_Smul: + case Id_Umul: case Id_Assert: // No output case Id_Assume: // No output case Id_Cover: // No output @@ -443,6 +445,12 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Asr: module->addSshr(to_str(iname), IN(0), IN(1), OUT(0), true); break; + case Id_Smul: + module->addMul(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Umul: + module->addMul(to_str(iname), IN(0), IN(1), OUT(0), false); + break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); break; diff --git a/testsuite/pr64/testsuite.sh b/testsuite/pr64/testsuite.sh new file mode 100755 index 0000000..7c3865a --- /dev/null +++ b/testsuite/pr64/testsuite.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +. ../testenv.sh + +run_yosys -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il" + +grep -q 11111111111011110000000000100000000000001101111111110000000000000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1 +grep -q 00000000000000000000000000001111111111111110111111110000000100000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1 + +clean diff --git a/testsuite/pr64/vector.vhdl b/testsuite/pr64/vector.vhdl new file mode 100644 index 0000000..c88c117 --- /dev/null +++ b/testsuite/pr64/vector.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port ( + s : out signed(127 downto 0); + u : out unsigned(127 downto 0) + ); +end entity vector; + +architecture synth of vector is +begin + s <= signed'(x"ffff000000fffff0") * signed'(x"fff0000ffff00000"); + u <= unsigned'(x"ffff000000fffff0") * unsigned'(x"fff0000ffff00000"); +end synth; |