4 files changed, 134 insertions, 0 deletions
diff --git a/library/wrapper/README b/library/wrapper/README
new file mode 100644
index 0000000..29550f0
--- /dev/null
+++ b/library/wrapper/README
@@ -0,0 +1,4 @@
+This directory should leave - in future.
+
+It contains hand woven Verilog wrappers for non resolving entities or
+primitives with generics.
diff --git a/library/wrapper/bram.v b/library/wrapper/bram.v
new file mode 100644
index 0000000..03859dc
--- /dev/null
+++ b/library/wrapper/bram.v
@@ -0,0 +1,46 @@
+// Workaround BRAM implementation for fifo buffer
+// 2020 <hackfin@section5.ch>
+
+module bram_2psync_6_8_59fe624214af9b8daa183282288d5eb56b321f14 #(
+	parameter DATA = 8,
+	parameter ADDR = 6
+) (
+
+	// Port A
+	input	wire				clk,
+	input	wire				a_we,
+	input	wire	[ADDR-1:0]	a_addr,
+	input	wire	[DATA-1:0]	a_write,
+	output	reg		[DATA-1:0]	a_read,
+
+	// Port B
+	input	wire				b_we,
+	input	wire	[ADDR-1:0]	b_addr,
+	input	wire	[DATA-1:0]	b_write,
+	output	reg		[DATA-1:0]	b_read
+);
+
+// Shared memory
+reg [DATA-1:0] mem [(2**ADDR)-1:0];
+
+reg [ADDR-1:0] addr_b;
+reg [ADDR-1:0] addr_a;
+
+
+assign a_read = mem[addr_a];
+// assign b_read = mem[addr_b];
+
+always @(posedge clk) begin: DUAL_RAW_PORT_A_PROC
+    addr_a <= a_addr;
+end
+
+
+always @(posedge clk) begin: DUAL_RAW_PORT_B_PROC
+    addr_b <= b_addr;
+    if (b_we) begin
+        mem[b_addr] <= b_write;
+    end
+end
+
+
+endmodule
diff --git a/library/wrapper/primitives.v b/library/wrapper/primitives.v
new file mode 100644
index 0000000..95edf7a
--- /dev/null
+++ b/library/wrapper/primitives.v
@@ -0,0 +1,13 @@
+`timescale 1 ns / 1 ps
+
+module vhi ( z );
+    output z ;
+  supply1 VSS;
+  buf (z , VSS);
+endmodule 
+
+module vlo ( z );
+	output z;
+  supply1 VSS;
+  buf (z , VSS);
+endmodule
diff --git a/library/wrapper/wrapper.v b/library/wrapper/wrapper.v
new file mode 100644
index 0000000..8f6d9cc
--- /dev/null
+++ b/library/wrapper/wrapper.v
@@ -0,0 +1,71 @@
+// Wrapper for specific instantiation of EHXPLLL
+//
+// This is a workaround until we can automatically pass generics to
+// instanced vendor primitives (black boxes)
+//
+module ehxplll_4_5_6_30_15_10_5_29_14_9_0_0_0_0_0_0_0_200_df43956727cb406e91ea03c3249c0f9d5327137e(clki, clkfb, phasesel1, phasesel0, phasedir, phasestep, phaseloadreg, stdby, 
+   pllwakesync, rst, enclkop, enclkos, enclkos2, enclkos3, 
+   clkop, clkos, clkos2, clkos3, lock, intlock, 
+   refclk, clkintfb );
+
+input  clki, clkfb, phasesel1, phasesel0, phasedir, phasestep;
+input  phaseloadreg, stdby, pllwakesync, rst;
+input  enclkop, enclkos, enclkos2, enclkos3;
+output clkop, clkos, clkos2, clkos3, lock, intlock, refclk;
+output clkintfb;
+
+	wire clkop_int;
+
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(4),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(6),
+        .CLKOP_CPHASE(5),
+        .CLKOP_FPHASE(0),
+        // .CLKOP_TRIM_DELAY(0),
+        .CLKOP_TRIM_POL("FALLING"),
+        .CLKOS_ENABLE("ENABLED"),
+        .CLKOS_DIV(30),
+        .CLKOS_CPHASE(29),
+        .CLKOS_FPHASE(0),
+        // .CLKOS_TRIM_DELAY(0),
+        .CLKOS_TRIM_POL("FALLING"),
+        .CLKOS2_ENABLE("ENABLED"),
+        .CLKOS2_DIV(15),
+        .CLKOS2_CPHASE(14),
+        .CLKOS2_FPHASE(0),
+        .CLKOS3_ENABLE("ENABLED"),
+        .CLKOS3_DIV(10),
+        .CLKOS3_CPHASE(9),
+        .CLKOS3_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(5)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clki),
+        .CLKOP(clkop_int),
+        .CLKOS(clkos),
+        .CLKFB(clkop_int),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(lock)
+	);
+
+	assign clkop = clkop_int;
+
+endmodule