From 31c421981e03ef1861887507a9f19e2076a87fdb Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 15 Feb 2017 12:22:54 +0100
Subject: ice40hx8k/spin1.vhdl: assign all outputs.

---
 ice40hx8k/spin1.vhdl                  |  3 +++
 testsuite/test-ice40hx8k/testsuite.sh | 12 ++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100755 testsuite/test-ice40hx8k/testsuite.sh

diff --git a/ice40hx8k/spin1.vhdl b/ice40hx8k/spin1.vhdl
index 79e305c..7c50586 100644
--- a/ice40hx8k/spin1.vhdl
+++ b/ice40hx8k/spin1.vhdl
@@ -4,6 +4,9 @@ architecture spin1 of leds is
   signal leds : std_ulogic_vector (1 to 5);
 begin
   (led1, led2, led3, led4, led5) <= leds;
+  led6 <= '0';
+  led7 <= '0';
+  led8 <= '0';
 
   process (clk)
     variable cnt : unsigned (1 downto 0) := "00";
diff --git a/testsuite/test-ice40hx8k/testsuite.sh b/testsuite/test-ice40hx8k/testsuite.sh
new file mode 100755
index 0000000..be1bf88
--- /dev/null
+++ b/testsuite/test-ice40hx8k/testsuite.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+. ../testenv.sh
+
+analyze ../../ice40hx8k/leds.vhdl
+analyze ../../ice40hx8k/spin1.vhdl
+synth leds
+
+analyze ../../ice40hx8k/spin2.vhdl
+synth leds
+
+clean
-- 
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