From de1a576d22c27df2e6e66335fce81e35b56f3d67 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 3 Dec 2019 21:04:15 +0100
Subject: Add test for #75

---
 testsuite/issues/issue75/testsuite.sh |  9 +++++++
 testsuite/issues/issue75/top.vhdl     | 46 +++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100755 testsuite/issues/issue75/testsuite.sh
 create mode 100644 testsuite/issues/issue75/top.vhdl

diff --git a/testsuite/issues/issue75/testsuite.sh b/testsuite/issues/issue75/testsuite.sh
new file mode 100755
index 0000000..408584f
--- /dev/null
+++ b/testsuite/issues/issue75/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl top.vhdl -e top; hierarchy -check -top top"
+
+clean
+echo OK
diff --git a/testsuite/issues/issue75/top.vhdl b/testsuite/issues/issue75/top.vhdl
new file mode 100644
index 0000000..0e0b602
--- /dev/null
+++ b/testsuite/issues/issue75/top.vhdl
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity child is
+  port (
+    CLK: in std_logic;
+    I: in std_logic;
+    O: out std_logic
+  );
+end entity child;
+
+architecture rtl of child is
+  signal Ialias: std_logic;
+begin
+  process (CLK)
+  begin
+    if rising_edge(CLK) then
+      O <= Ialias;
+    end if;
+  end process;
+  Ialias <= I;
+end architecture rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity top is
+  port (
+    CLK: in std_logic;
+    I: in std_logic;
+    O: out std_logic
+  );
+end entity top;
+
+architecture rtl of top is
+  component child is
+    port (
+      CLK: in std_logic;
+      I: in std_logic;
+      O: out std_logic
+    );
+  end component child;
+begin
+  inst : child port map(CLK, I, O);
+end architecture rtl;
-- 
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