From ef286d8f3e02f7ef5b227f28e66b05122d816129 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 31 Mar 2020 18:39:09 +0200
Subject: Adjust ecp5_versa tests.  Wrappers for verilog modules are not needed
 anymore.

---
 examples/ecp5_versa/Makefile | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

(limited to 'examples/ecp5_versa/Makefile')

diff --git a/examples/ecp5_versa/Makefile b/examples/ecp5_versa/Makefile
index 6031055..2b54e17 100644
--- a/examples/ecp5_versa/Makefile
+++ b/examples/ecp5_versa/Makefile
@@ -21,10 +21,9 @@ VHDL_SYN_FILES += soc_iomap_pkg.vhdl
 VHDL_SYN_FILES += uart.vhdl uart_tx.vhdl uart_rx.vhdl fifobuf.vhdl
 
 TOPLEVEL = versa_ecp5_top
-TOPLEVEL_PARAMETER = _$(CLK_FREQ)
+TOPLEVEL_PARAMETER =
 
 VERILOG_FILES = $(LIB)/wrapper/primitives.v
-VERILOG_FILES += $(LIB)/wrapper/wrapper.v
 VERILOG_FILES += $(LIB)/wrapper/bram.v
 
 SVFFILE = versa_ecp5_top.svf
@@ -39,10 +38,9 @@ lib:
 	mkdir $@
 
 lib/ecp5um-std93.cf: $(LIB)/ecp5u/components.vhdl | lib
-	$(GHDL) -i --workdir=$(dir $@) --work=ecp5um \
-		$< 
+	$(GHDL) -i --workdir=$(dir $@) --work=ecp5um $<
 
-pll_mac.vhd: $(DEPENDENCIES) 
+pll_mac.vhd: $(DEPENDENCIES)
 
 prog: $(SVFFILE)
 	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) \
-- 
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