From ef286d8f3e02f7ef5b227f28e66b05122d816129 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 31 Mar 2020 18:39:09 +0200
Subject: Adjust ecp5_versa tests.  Wrappers for verilog modules are not needed
 anymore.

---
 examples/ecp5_versa/Makefile     |  8 +++-----
 examples/ecp5_versa/fifobuf.vhdl | 20 +++++++++-----------
 2 files changed, 12 insertions(+), 16 deletions(-)

(limited to 'examples')

diff --git a/examples/ecp5_versa/Makefile b/examples/ecp5_versa/Makefile
index 6031055..2b54e17 100644
--- a/examples/ecp5_versa/Makefile
+++ b/examples/ecp5_versa/Makefile
@@ -21,10 +21,9 @@ VHDL_SYN_FILES += soc_iomap_pkg.vhdl
 VHDL_SYN_FILES += uart.vhdl uart_tx.vhdl uart_rx.vhdl fifobuf.vhdl
 
 TOPLEVEL = versa_ecp5_top
-TOPLEVEL_PARAMETER = _$(CLK_FREQ)
+TOPLEVEL_PARAMETER =
 
 VERILOG_FILES = $(LIB)/wrapper/primitives.v
-VERILOG_FILES += $(LIB)/wrapper/wrapper.v
 VERILOG_FILES += $(LIB)/wrapper/bram.v
 
 SVFFILE = versa_ecp5_top.svf
@@ -39,10 +38,9 @@ lib:
 	mkdir $@
 
 lib/ecp5um-std93.cf: $(LIB)/ecp5u/components.vhdl | lib
-	$(GHDL) -i --workdir=$(dir $@) --work=ecp5um \
-		$< 
+	$(GHDL) -i --workdir=$(dir $@) --work=ecp5um $<
 
-pll_mac.vhd: $(DEPENDENCIES) 
+pll_mac.vhd: $(DEPENDENCIES)
 
 prog: $(SVFFILE)
 	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) \
diff --git a/examples/ecp5_versa/fifobuf.vhdl b/examples/ecp5_versa/fifobuf.vhdl
index 4981c1d..8122839 100644
--- a/examples/ecp5_versa/fifobuf.vhdl
+++ b/examples/ecp5_versa/fifobuf.vhdl
@@ -62,21 +62,20 @@ architecture behaviour of FifoBuffer is
 
 	component bram_2psync is
 		generic (
-			ADDR_W      : natural := 6;
-			DATA_W      : natural := 16;
-			SYN_RAMTYPE : string := "block_ram"
+			ADDR      : natural := 6;
+			DATA      : natural := 16
 		);
 		port (
 			-- Port A
 			a_we    : in  std_logic;
-			a_addr  : in  unsigned(ADDR_W-1 downto 0);
-			a_write : in  unsigned(DATA_W-1 downto 0);
-			a_read  : out unsigned(DATA_W-1 downto 0);
+			a_addr  : in  unsigned(ADDR-1 downto 0);
+			a_write : in  unsigned(DATA-1 downto 0);
+			a_read  : out unsigned(DATA-1 downto 0);
 			-- Port B
 			b_we    : in  std_logic;
-			b_addr  : in  unsigned(ADDR_W-1 downto 0);
-			b_write : in  unsigned(DATA_W-1 downto 0);
-			b_read  : out unsigned(DATA_W-1 downto 0);
+			b_addr  : in  unsigned(ADDR-1 downto 0);
+			b_write : in  unsigned(DATA-1 downto 0);
+			b_read  : out unsigned(DATA-1 downto 0);
 			clk     : in  std_logic
 		);
 	end component bram_2psync;
@@ -160,8 +159,7 @@ fsm:
 
 ram:
 	bram_2psync
-	generic map ( ADDR_W => ADDR_W, DATA_W => DATA_W,
-		SYN_RAMTYPE => SYN_RAMTYPE)
+	generic map ( ADDR => ADDR_W, DATA => DATA_W)
 	port map (
 		a_we    => '0',
 		a_addr  => optr,
-- 
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