From b6e2889c604c07dc3f4d2fde5aed1b29e1285e25 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 31 Jul 2019 20:38:39 +0200 Subject: add signed compare (#29) --- ghdl/ghdl.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'ghdl/ghdl.cc') diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index b2a2cf7..6926cfd 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -271,6 +271,10 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Ule: case Id_Ugt: case Id_Uge: + case Id_Slt: + case Id_Sle: + case Id_Sgt: + case Id_Sge: case Id_Not: case Id_Red_Or: case Id_Red_And: @@ -374,6 +378,18 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Uge: module->addGe(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Slt: + module->addLt(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Sle: + module->addLe(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Sgt: + module->addGt(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Sge: + module->addGe(to_str(iname), IN(0), IN(1), OUT(0), true); + break; case Id_Red_Or: module->addReduceOr(to_str(iname), IN(0), OUT(0)); break; -- cgit v1.2.3