From 366d22bac43caec422b0628c08b5986b0199e4bf Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 2 Oct 2019 04:32:49 +0200
Subject: handle Const_Log

---
 src/ghdl.cc | 59 ++++++++++++++++++++++++++++++++++-------------------------
 1 file changed, 34 insertions(+), 25 deletions(-)

(limited to 'src/ghdl.cc')

diff --git a/src/ghdl.cc b/src/ghdl.cc
index 7615ccb..ed19b1a 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -81,32 +81,8 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n)
 			RTLIL::SigSpec res = IN(0);
 			return res.extract(0, get_width(n));
 		}
-	case Id_Const_UB32:
-		return SigSpec(get_param_uns32(inst, 0), get_width(n));
-	case Id_Const_UL32:
-		{
-		       std::vector<RTLIL::State> bits(get_width(n));
-		       unsigned int val01 = get_param_uns32(inst, 0);
-		       unsigned int valzx = get_param_uns32(inst, 1);
-		       for (unsigned int i = 0; i < get_width(n); i++) {
-			switch(((val01 >> i)&1)+((valzx >> i)&1)*2) {
-			    case 0:
-				bits[i] = RTLIL::State::S0;
-				break;
-			    case 1:
-				bits[i] = RTLIL::State::S1;
-				break;
-			    case 2:
-				bits[i] = RTLIL::State::Sz;
-				break;
-			    case 3:
-				bits[i] = RTLIL::State::Sx;
-				break;
-			}
-		       }
-		       return RTLIL::SigSpec(RTLIL::Const(bits));
-		}
 	case Id_Const_Bit:
+	case Id_Const_UB32:
 		{
 		       const unsigned wd = get_width(n);
 		       std::vector<RTLIL::State> bits(wd);
@@ -118,6 +94,37 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n)
 		       }
 		       return RTLIL::SigSpec(RTLIL::Const(bits));
 		}
+	case Id_Const_Log:
+	case Id_Const_UL32:
+	        {
+		       const unsigned wd = get_width(n);
+		       std::vector<RTLIL::State> bits(wd);
+		       unsigned int val01;
+		       unsigned int valzx;
+		       for (unsigned i = 0; i < wd; i++) {
+			       if (i % 32 == 0) {
+			               val01 = get_param_uns32(inst, 2*(i / 32));
+				       valzx = get_param_uns32(inst, 2*(i / 32) + 1);
+			       }
+			       switch(((val01 >> i)&1)+((valzx >> i)&1)*2)
+			       {
+			       case 0:
+			               bits[i] = RTLIL::State::S0;
+				       break;
+			       case 1:
+				       bits[i] = RTLIL::State::S1;
+				       break;
+			       case 2:
+				       bits[i] = RTLIL::State::Sz;
+				       break;
+			       case 3:
+				       bits[i] = RTLIL::State::Sx;
+				       break;
+			       }
+
+		       }
+		       return RTLIL::SigSpec(RTLIL::Const(bits));
+		}
 	case Id_Extract:
 		{
 			RTLIL::SigSpec res = IN(0);
@@ -303,6 +310,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 		case Id_Const_UB32:
 		case Id_Const_UL32:
 		case Id_Const_Bit:
+		case Id_Const_Log:
 		case Id_Uextend:
 		case Id_Utrunc:
 		case Id_Strunc:
@@ -476,6 +484,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 		case Id_Const_UB32:
 		case Id_Const_UL32:
 		case Id_Const_Bit:
+		case Id_Const_Log:
 		case Id_Uextend:
 		case Id_Utrunc:
 		case Id_Strunc:
-- 
cgit v1.2.3