From 768e1f7a45ae1c818eea631d5a8fb79775e34108 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 7 Apr 2020 06:45:02 +0200
Subject: Add support for smod.  Fix #102

---
 src/ghdl.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/ghdl.cc')

diff --git a/src/ghdl.cc b/src/ghdl.cc
index 834553e..c1cab92 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -622,6 +622,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 		case Id_Sdiv:
 		case Id_Udiv:
 		case Id_Srem:
+		case Id_Smod:
 		case Id_Umod:
 		case Id_Allconst:
 		case Id_Allseq:
@@ -821,6 +822,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 			module->addDiv(to_str(iname), IN(0), IN(1), OUT(0), false);
 			break;
 		case Id_Srem:
+		case Id_Smod:
 			// Yosys modulus usese Verilogs *remainder* behavior
 			// there is no signed modulus operator in Yosys
 			module->addMod(to_str(iname), IN(0), IN(1), OUT(0), true);
-- 
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