From 0ac58d2a569dae3db5d53c70750c5cb0b535ce8b Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Sun, 3 Nov 2019 17:54:04 +0100 Subject: add iadff (#67) --- src/ghdl.cc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/ghdl.cc b/src/ghdl.cc index 94a185c..d2d33e6 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -491,8 +491,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Mux2: case Id_Mux4: case Id_Dff: - case Id_Adff: case Id_Idff: + case Id_Adff: + case Id_Iadff: case Id_Eq: case Id_Ne: case Id_Ult: @@ -684,7 +685,13 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) } break; case Id_Adff: + case Id_Iadff: module->addAdff(to_str(iname), IN(0), IN(2), IN(1), OUT(0), IN(3).as_const()); + // For iadff, the initial value is set on the output + // wire. + if (id == Id_Iadff) { + net_map[get_output(inst, 0).id]->attributes["\\init"] = IN(2).as_const(); + } break; case Id_Mux4: { -- cgit v1.2.3