From 8e1a7aac07bdddeec71614574e886c9438848bb2 Mon Sep 17 00:00:00 2001 From: rlee287 Date: Wed, 27 May 2020 12:49:42 -0700 Subject: Add reduce_xor support to the Yosys plugin This is a followup for ghdl/ghdl issue 1342 --- src/ghdl.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/ghdl.cc b/src/ghdl.cc index 0d91bb4..d1e5cd8 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -663,6 +663,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Abs: case Id_Red_Or: case Id_Red_And: + case Id_Red_Xor: case Id_Lsr: case Id_Lsl: case Id_Asr: @@ -840,6 +841,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Red_And: module->addReduceAnd(to_str(iname), IN(0), OUT(0)); break; + case Id_Red_Xor: + module->addReduceXor(to_str(iname), IN(0), OUT(0)); + break; case Id_Lsl: module->addShl(to_str(iname), IN(0), IN(1), OUT(0)); break; -- cgit v1.2.3