From 9a8c8162b869479017ccb6f642fadce717685fa3 Mon Sep 17 00:00:00 2001 From: "T. Meissner" Date: Wed, 9 Oct 2019 18:33:15 +0200 Subject: Handle Id_Sextend (#59) --- src/ghdl.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/ghdl.cc b/src/ghdl.cc index 58c738e..83b76d0 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -75,6 +75,12 @@ static RTLIL::SigSpec get_src(std::vector &net_map, Net n) res.extend_u0(get_width(n), false); return res; } + case Id_Sextend: + { + RTLIL::SigSpec res = IN(0); + res.extend_u0(get_width(n), true); + return res; + } case Id_Utrunc: case Id_Strunc: { @@ -325,6 +331,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_Z: case Id_Const_X: case Id_Uextend: + case Id_Sextend: case Id_Utrunc: case Id_Strunc: case Id_Extract: @@ -510,6 +517,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_Z: case Id_Const_X: case Id_Uextend: + case Id_Sextend: case Id_Utrunc: case Id_Strunc: case Id_Extract: -- cgit v1.2.3