From ba8da81f036d761adbb69331d666bc90b3b3bf11 Mon Sep 17 00:00:00 2001 From: "T. Meissner" Date: Fri, 20 Sep 2019 03:48:49 +0200 Subject: Handle covers (#43) --- src/ghdl.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/ghdl.cc b/src/ghdl.cc index 421f1b4..a758928 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -272,6 +272,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Red_And: case Id_Assert: // No output case Id_Assume: // No output + case Id_Cover: // No output case Id_User_None: for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { Net o = get_output(inst, idx); @@ -456,6 +457,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Assume: module->addAssume(to_str(iname), IN(0), State::S1); break; + case Id_Cover: + module->addCover(to_str(iname), IN(0), State::S1); + break; case Id_Const_UB32: case Id_Const_UL32: case Id_Uextend: -- cgit v1.2.3