From d216549165da5496da30ce0a28fcf5c2a36a3278 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 8 Apr 2020 22:29:46 +0200 Subject: Fix signed modulo behaviour Yosys' $mod cell is the modulo of truncating division, known as "rem" in VHDL. The new $modfloor cell is the modulo of flooring division, known as "mod" in VHDL. "mod" now synthesizes correctly for negative numbers. --- src/ghdl.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/ghdl.cc b/src/ghdl.cc index d1e5cd8..becce24 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -883,13 +883,14 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) module->addDiv(to_str(iname), IN(0), IN(1), OUT(0), false); break; case Id_Srem: - case Id_Smod: - // Yosys modulus uses Verilogs *remainder* behavior - // there is no signed modulus operator in Yosys + // Id_Urem would be the same as Id_Umod, so only the latter exists + // $mod: modulo of truncating division, "rem" in VHDL module->addMod(to_str(iname), IN(0), IN(1), OUT(0), true); break; + case Id_Smod: case Id_Umod: - module->addMod(to_str(iname), IN(0), IN(1), OUT(0), false); + // $modfloor: modulo of flooring division, "mod" in VHDL + module->addModFloor(to_str(iname), IN(0), IN(1), OUT(0), id == Id_Smod); break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); -- cgit v1.2.3