From d941c8f65bbbb90f97c17e26b5610624c2198b10 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 15 Apr 2020 07:37:15 +0200 Subject: Add tests/examples for dff (both pos and neg edge). --- testsuite/examples/dff/adff.vhdl | 23 +++++++++++++++++++++++ testsuite/examples/dff/dff.vhdl | 20 ++++++++++++++++++++ testsuite/examples/dff/negadff.vhdl | 23 +++++++++++++++++++++++ testsuite/examples/dff/negdff.vhdl | 20 ++++++++++++++++++++ testsuite/examples/dff/testsuite.sh | 30 ++++++++++++++++++++++++++++++ 5 files changed, 116 insertions(+) create mode 100644 testsuite/examples/dff/adff.vhdl create mode 100644 testsuite/examples/dff/dff.vhdl create mode 100644 testsuite/examples/dff/negadff.vhdl create mode 100644 testsuite/examples/dff/negdff.vhdl create mode 100755 testsuite/examples/dff/testsuite.sh (limited to 'testsuite/examples') diff --git a/testsuite/examples/dff/adff.vhdl b/testsuite/examples/dff/adff.vhdl new file mode 100644 index 0000000..f5638b8 --- /dev/null +++ b/testsuite/examples/dff/adff.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity adff is + port( + clk : in std_logic; + rst : in std_logic; + d : in std_logic; + q : out std_logic + ); +end entity; + +architecture arch of adff is +begin + process (clk, rst) + begin + if rst = '1' then + q <= '1'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; +end architecture; diff --git a/testsuite/examples/dff/dff.vhdl b/testsuite/examples/dff/dff.vhdl new file mode 100644 index 0000000..3f47af3 --- /dev/null +++ b/testsuite/examples/dff/dff.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff is + port( + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end entity; + +architecture arch of dff is +begin + process (clk) + begin + if rising_edge(clk) then + q <= d; + end if; + end process; +end architecture; diff --git a/testsuite/examples/dff/negadff.vhdl b/testsuite/examples/dff/negadff.vhdl new file mode 100644 index 0000000..5f1fb0a --- /dev/null +++ b/testsuite/examples/dff/negadff.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity negadff is + port( + clk : in std_logic; + rst : in std_logic; + d : in std_logic; + q : out std_logic + ); +end entity; + +architecture arch of negadff is +begin + process (clk, rst) + begin + if rst = '1' then + q <= '0'; + elsif falling_edge(clk) then + q <= d; + end if; + end process; +end architecture; diff --git a/testsuite/examples/dff/negdff.vhdl b/testsuite/examples/dff/negdff.vhdl new file mode 100644 index 0000000..2d2fb11 --- /dev/null +++ b/testsuite/examples/dff/negdff.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity negdff is + port( + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end entity; + +architecture arch of negdff is +begin + process (clk) + begin + if falling_edge(clk) then + q <= d; + end if; + end process; +end architecture; diff --git a/testsuite/examples/dff/testsuite.sh b/testsuite/examples/dff/testsuite.sh new file mode 100755 index 0000000..aceef4e --- /dev/null +++ b/testsuite/examples/dff/testsuite.sh @@ -0,0 +1,30 @@ +#!/bin/sh + +topdir=../.. +. $topdir/testenv.sh + +run_yosys -q -p "ghdl negdff.vhdl -e; write_ilang negdff.ilang" +fgrep -q "cell \$dff" negdff.ilang +fgrep -q "CLK_POLARITY 0" negdff.ilang +fgrep -q "WIDTH 1" negdff.ilang + +run_yosys -q -p "ghdl dff.vhdl -e; write_ilang dff.ilang" +fgrep -q "CLK_POLARITY 1" dff.ilang +fgrep -q "WIDTH 1" dff.ilang + +run_yosys -q -p "ghdl adff.vhdl -e; opt; write_ilang adff.ilang" +fgrep -q 'cell $adff' adff.ilang +fgrep -q 'ARST_POLARITY 1' adff.ilang +fgrep -q "ARST_VALUE 1'1" adff.ilang +fgrep -q 'CLK_POLARITY 1' adff.ilang +fgrep -q 'WIDTH 1' adff.ilang + +run_yosys -q -p "ghdl negadff.vhdl -e; write_ilang negadff.ilang" +fgrep -q 'cell $adff' negadff.ilang +fgrep -q 'ARST_POLARITY 1' negadff.ilang +fgrep -q "ARST_VALUE 1'0" negadff.ilang +fgrep -q 'CLK_POLARITY 0' negadff.ilang +fgrep -q 'WIDTH 1' negadff.ilang + +clean +echo OK -- cgit v1.2.3