From ef286d8f3e02f7ef5b227f28e66b05122d816129 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 31 Mar 2020 18:39:09 +0200 Subject: Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore. --- testsuite/examples/test-ecp5_versa/testsuite.sh | 1 - 1 file changed, 1 deletion(-) (limited to 'testsuite/examples') diff --git a/testsuite/examples/test-ecp5_versa/testsuite.sh b/testsuite/examples/test-ecp5_versa/testsuite.sh index 44dac88..8574b94 100755 --- a/testsuite/examples/test-ecp5_versa/testsuite.sh +++ b/testsuite/examples/test-ecp5_versa/testsuite.sh @@ -16,7 +16,6 @@ VHDL_SYN_FILES="$src/versa_ecp5_top.vhdl \ VERILOG_FILES="\ $top/library/wrapper/primitives.v \ - $top/library/wrapper/wrapper.v \ $top/library/wrapper/bram.v " -- cgit v1.2.3