From d6a6572439a1f3d7d8c55ae181b978d693ab85d2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 2 Oct 2021 19:21:00 +0200 Subject: testsuite: add a test for #158 --- testsuite/issues/issue158/repro.vhdl | 43 ++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 testsuite/issues/issue158/repro.vhdl (limited to 'testsuite/issues/issue158/repro.vhdl') diff --git a/testsuite/issues/issue158/repro.vhdl b/testsuite/issues/issue158/repro.vhdl new file mode 100644 index 0000000..d695bb0 --- /dev/null +++ b/testsuite/issues/issue158/repro.vhdl @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity MUX_uint4 is + port( + iftrue : in std_logic_vector(3 downto 0); + return_output : out std_logic_vector(3 downto 0)); +end; +architecture arch of MUX_uint4 is +begin + return_output <= iftrue; +end arch; + +library ieee; +use ieee.std_logic_1164.all; + +entity repro is + port( + clk : in std_logic; + module_to_clk_cross : out std_ulogic); +end; + +architecture arch of repro is + type variables_t is record + iftrue : std_logic_vector(3 downto 0); + return_output : std_logic_vector(3 downto 0); + end record; + + signal iftrue : std_logic_vector(3 downto 0); + signal return_output : std_logic_vector(3 downto 0); +begin + c3_8e8a : entity work.MUX_uint4 port map (iftrue, return_output); + + process (clk) is + variable read_pipe : variables_t; + variable write_pipe : variables_t; + begin + write_pipe := read_pipe; + iftrue <= write_pipe.iftrue; + -- write_pipe.return_output := return_output; + read_pipe := write_pipe; + end process; +end arch; -- cgit v1.2.3