From 73e03cbc9b07dbc1bfc75be3baf8fd9fc66e32d8 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 4 Nov 2019 20:41:57 +0100
Subject: Add testcase for #68

---
 testsuite/issues/issue68/demux.vhdl | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 testsuite/issues/issue68/demux.vhdl

(limited to 'testsuite/issues/issue68/demux.vhdl')

diff --git a/testsuite/issues/issue68/demux.vhdl b/testsuite/issues/issue68/demux.vhdl
new file mode 100644
index 0000000..936a38d
--- /dev/null
+++ b/testsuite/issues/issue68/demux.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity demux is port (
+   j :  in integer range 0 to 3;
+   k :  in std_logic;
+   l :  in std_logic;
+   y : out std_logic_vector(1 to 5));
+end demux;
+
+architecture beh of demux is
+
+   function to_slv(C:integer; B:std_logic; E:std_logic) return std_logic_vector is
+   variable ret : std_logic_vector(1 to 5) := (others => '0');
+   begin
+      ret(C+1) := E;
+      ret(5)   := B;
+
+      return ret;
+   end to_slv;
+begin
+   y <= to_slv(j, k, l);
+end beh;
-- 
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