From 0833d3f90a29f0bce364833f20430968deeee0b7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 5 Dec 2019 22:32:49 +0100
Subject: Add testcase for #73

---
 testsuite/issues/issue73/cell2.vhdl | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 testsuite/issues/issue73/cell2.vhdl

(limited to 'testsuite/issues/issue73/cell2.vhdl')

diff --git a/testsuite/issues/issue73/cell2.vhdl b/testsuite/issues/issue73/cell2.vhdl
new file mode 100644
index 0000000..e55aac2
--- /dev/null
+++ b/testsuite/issues/issue73/cell2.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell2 is
+  port (
+    O: out std_logic
+  );
+end entity cell2;
+
+architecture rtl of cell2 is
+begin
+  O <= '1';
+end architecture rtl;
-- 
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