From a5b45005f091ab16c108279a0c15334efc0347d3 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 27 Sep 2020 09:56:42 +0200 Subject: testsuite/issues: renames pr61 to issue61 --- testsuite/issues/pr61/vector.vhdl | 20 -------------------- 1 file changed, 20 deletions(-) delete mode 100644 testsuite/issues/pr61/vector.vhdl (limited to 'testsuite/issues/pr61/vector.vhdl') diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl deleted file mode 100644 index 34274be..0000000 --- a/testsuite/issues/pr61/vector.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity vector is - port (v: out signed(63 downto 0); - u: out unsigned(63 downto 0)); -end vector; - -architecture synth of vector is - signal v1 : signed (63 downto 0); - signal u1 : unsigned (63 downto 0); - -begin - v1 <= x"0ffffffffffffff0"; - v <= v1+(-1); - u1 <= x"00ffffffffffff00"; --- u <= u1 + (-6); -- +4294967290; - u <= u1 + 6; -end synth; -- cgit v1.2.3