From 70acfa684c7752dd836d4bf95c4b7d4d83053592 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 5 Nov 2019 04:44:55 +0100
Subject: testsuite: move pr tests in issues/

---
 testsuite/issues/pr66/testsuite.sh | 12 ++++++++++++
 testsuite/issues/pr66/vector.vhdl  | 14 ++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100755 testsuite/issues/pr66/testsuite.sh
 create mode 100644 testsuite/issues/pr66/vector.vhdl

(limited to 'testsuite/issues/pr66')

diff --git a/testsuite/issues/pr66/testsuite.sh b/testsuite/issues/pr66/testsuite.sh
new file mode 100755
index 0000000..6d8bc7e
--- /dev/null
+++ b/testsuite/issues/pr66/testsuite.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 'connect \\v 63' vector.il || exit 1
+
+clean
+rm  vector.il
+echo OK
diff --git a/testsuite/issues/pr66/vector.vhdl b/testsuite/issues/pr66/vector.vhdl
new file mode 100644
index 0000000..3eb9951
--- /dev/null
+++ b/testsuite/issues/pr66/vector.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (v: out integer
+          );
+end vector;
+
+architecture synth of vector is
+
+begin
+    v <= to_integer(unsigned'(x"7fffffff")) mod 64;
+end synth;
-- 
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