From 016591a902e5746986244064c12183847f2f1101 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 6 Nov 2019 03:57:59 +0100
Subject: Add testcase from issue 1001

---
 testsuite/ghdl-issues/issue1001/async.vhdl   | 35 ++++++++++++++++++++++++++
 testsuite/ghdl-issues/issue1001/sync.vhdl    | 37 ++++++++++++++++++++++++++++
 testsuite/ghdl-issues/issue1001/testsuite.sh | 10 ++++++++
 3 files changed, 82 insertions(+)
 create mode 100644 testsuite/ghdl-issues/issue1001/async.vhdl
 create mode 100644 testsuite/ghdl-issues/issue1001/sync.vhdl
 create mode 100755 testsuite/ghdl-issues/issue1001/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/ghdl-issues/issue1001/async.vhdl b/testsuite/ghdl-issues/issue1001/async.vhdl
new file mode 100644
index 0000000..d2c4707
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1001/async.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+  port (
+    Reset_n_i    : in  std_logic;
+    Clk_i        : in  std_logic;
+    Wen_i        : in  std_logic;
+    Addr_i       : in  natural range 0 to 2**8-1;
+    Din_i        : in  std_logic_vector(7 downto 0);
+    Dout_o       : out std_logic_vector(7 downto 0)
+  );
+end entity test;
+
+architecture rtl of test is
+
+  type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
+  signal s_register : t_register;
+
+begin
+
+  Dout_o <= s_register(Addr_i);
+
+  WriteP : process (Clk_i, Reset_n_i) is
+  begin
+    if Reset_n_i = '0' then
+      s_register <= (others => (others => '0'));
+    elsif rising_edge(Clk_i) then
+      if Wen_i = '1' then
+        s_register(Addr_i) <= Din_i;
+      end if;
+    end if;
+  end process WriteP;
+
+end architecture rtl;
diff --git a/testsuite/ghdl-issues/issue1001/sync.vhdl b/testsuite/ghdl-issues/issue1001/sync.vhdl
new file mode 100644
index 0000000..2a21371
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1001/sync.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+  port (
+    Reset_n_i    : in  std_logic;
+    Clk_i        : in  std_logic;
+    Wen_i        : in  std_logic;
+    Addr_i       : in  natural range 0 to 2**8-1;
+    Din_i        : in  std_logic_vector(7 downto 0);
+    Dout_o       : out std_logic_vector(7 downto 0)
+  );
+end entity test;
+
+architecture rtl of test is
+
+  type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
+  signal s_register : t_register;
+
+begin
+
+  Dout_o <= s_register(Addr_i);
+
+  WriteP : process (Clk_i) is
+  begin
+    if rising_edge(Clk_i) then
+      if Reset_n_i = '0' then
+        s_register <= (others => (others => '0'));
+      else
+        if Wen_i = '1' then
+          s_register(Addr_i) <= Din_i;
+        end if;
+      end if;
+    end if;
+  end process WriteP;
+
+end architecture rtl;
diff --git a/testsuite/ghdl-issues/issue1001/testsuite.sh b/testsuite/ghdl-issues/issue1001/testsuite.sh
new file mode 100755
index 0000000..dc4749c
--- /dev/null
+++ b/testsuite/ghdl-issues/issue1001/testsuite.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import sync.vhdl -e
+synth_import async.vhdl -e
+
+clean
+echo OK
-- 
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