From 8b220d2f18e12ef72879c44e0e105672a3e860df Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 5 Dec 2019 22:37:13 +0100
Subject: Add more tests for issue#36

---
 testsuite/issues/issue36/bram2.vhdl   | 36 +++++++++++++++++++++++++++++++++++
 testsuite/issues/issue36/bram3.vhdl   | 33 ++++++++++++++++++++++++++++++++
 testsuite/issues/issue36/testsuite.sh |  2 ++
 3 files changed, 71 insertions(+)
 create mode 100644 testsuite/issues/issue36/bram2.vhdl
 create mode 100644 testsuite/issues/issue36/bram3.vhdl

(limited to 'testsuite')

diff --git a/testsuite/issues/issue36/bram2.vhdl b/testsuite/issues/issue36/bram2.vhdl
new file mode 100644
index 0000000..f7f9b34
--- /dev/null
+++ b/testsuite/issues/issue36/bram2.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity bram is
+  generic (
+    addr_width : integer := 8;
+    data_width : integer := 32
+  );
+  port (
+    clk      : in std_logic;
+    we       : in std_logic;
+    re       : in std_logic;
+    waddr    : in std_logic_vector(addr_width-1 downto 0);
+    raddr    : in std_logic_vector(addr_width-1 downto 0);
+    wdata    : in std_logic_vector(data_width-1 downto 0);
+    rdata    : out std_logic_vector(data_width-1 downto 0)
+  );
+end bram;
+
+architecture rtl of bram is
+  type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
+  signal mem : mem_type;
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if we = '1' then
+        mem(to_integer(unsigned(waddr))) <= wdata;
+      end if;
+      if re = '1' then
+        rdata <= mem(to_integer(unsigned(raddr)));
+      end if;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/issues/issue36/bram3.vhdl b/testsuite/issues/issue36/bram3.vhdl
new file mode 100644
index 0000000..949a68f
--- /dev/null
+++ b/testsuite/issues/issue36/bram3.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity bram is
+  generic (
+    addr_width : integer := 8;
+    data_width : integer := 32
+  );
+  port (
+    clk      : in std_logic;
+    we       : in std_logic;
+    waddr    : in std_logic_vector(addr_width-1 downto 0);
+    raddr    : in std_logic_vector(addr_width-1 downto 0);
+    wdata    : in std_logic_vector(data_width-1 downto 0);
+    rdata    : out std_logic_vector(data_width-1 downto 0)
+  );
+end bram;
+
+architecture rtl of bram is
+  type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
+  signal mem : mem_type;
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if we = '1' then
+        mem(to_integer(unsigned(waddr))) <= wdata;
+      end if;
+      rdata <= mem(to_integer(unsigned(raddr)));
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/issues/issue36/testsuite.sh b/testsuite/issues/issue36/testsuite.sh
index 4377ed3..902a3de 100755
--- a/testsuite/issues/issue36/testsuite.sh
+++ b/testsuite/issues/issue36/testsuite.sh
@@ -4,6 +4,8 @@ topdir=../..
 . $topdir/testenv.sh
 
 synth_import bram.vhdl -e
+synth_import bram2.vhdl -e
+synth_import bram3.vhdl -e
 
 clean
 echo OK
-- 
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