From e27db89e7e9f80e0c739e8fdb043a7dff72b0a0a Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 7 Nov 2019 07:26:49 +0100
Subject: Add testcase from #36

---
 testsuite/issues/issue36/bram.vhdl    | 33 +++++++++++++++++++++++++++++++++
 testsuite/issues/issue36/testsuite.sh |  9 +++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 testsuite/issues/issue36/bram.vhdl
 create mode 100755 testsuite/issues/issue36/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/issues/issue36/bram.vhdl b/testsuite/issues/issue36/bram.vhdl
new file mode 100644
index 0000000..fcfb98b
--- /dev/null
+++ b/testsuite/issues/issue36/bram.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity bram is
+  generic (
+    addr_width : integer := 9;
+    data_width : integer := 8
+  );
+  port (
+    clk      : in std_logic;
+    we       : in std_logic;
+    addr     : in std_logic_vector(addr_width-1 downto 0);
+    data_in  : in std_logic_vector(data_width-1 downto 0);
+    data_out : out std_logic_vector(data_width-1 downto 0)
+  );
+end bram;
+
+architecture rtl of bram is
+  type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
+  signal mem : mem_type;
+
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if we = '1' then
+        mem(to_integer(unsigned(addr))) <= data_in;
+      end if;
+    end if;
+  end process;
+  data_out <= mem(to_integer(unsigned(addr)));
+end rtl;
diff --git a/testsuite/issues/issue36/testsuite.sh b/testsuite/issues/issue36/testsuite.sh
new file mode 100755
index 0000000..4377ed3
--- /dev/null
+++ b/testsuite/issues/issue36/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import bram.vhdl -e
+
+clean
+echo OK
-- 
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