From e7432e0ba23e9eb78bb7a381ac4d34431d60b3a1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 5 Nov 2019 04:48:38 +0100
Subject: testsuite: add case for issue 999

---
 testsuite/ghdl-issues/issue999/test.vhdl    | 35 +++++++++++++++++++++++++++++
 testsuite/ghdl-issues/issue999/testsuite.sh |  8 +++++++
 2 files changed, 43 insertions(+)
 create mode 100644 testsuite/ghdl-issues/issue999/test.vhdl
 create mode 100755 testsuite/ghdl-issues/issue999/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/ghdl-issues/issue999/test.vhdl b/testsuite/ghdl-issues/issue999/test.vhdl
new file mode 100644
index 0000000..71357c3
--- /dev/null
+++ b/testsuite/ghdl-issues/issue999/test.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+    port(
+        clk          : in std_logic;
+
+        read_reg     : in std_ulogic_vector(4 downto 0);
+        read_data    : out std_ulogic_vector(63 downto 0);
+
+        write_enable : in std_ulogic;
+        write_reg    : in std_ulogic_vector(4 downto 0);
+        write_data   : in std_ulogic_vector(63 downto 0)
+        );
+end entity test;
+
+architecture behaviour of test is
+    type regfile is array(0 to 31) of std_ulogic_vector(63 downto 0);
+    signal registers : regfile := (others => (others => '0'));
+begin
+    register_write_0: process(clk)
+    begin
+        if rising_edge(clk) then
+            if write_enable = '1' then
+                registers(to_integer(unsigned(write_reg))) <= write_data;
+            end if;
+        end if;
+    end process register_write_0;
+
+    register_read_0: process(all)
+    begin
+        read_data <= registers(to_integer(unsigned(read_reg)));
+    end process register_read_0;
+end architecture behaviour;
diff --git a/testsuite/ghdl-issues/issue999/testsuite.sh b/testsuite/ghdl-issues/issue999/testsuite.sh
new file mode 100755
index 0000000..981976c
--- /dev/null
+++ b/testsuite/ghdl-issues/issue999/testsuite.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import --std=08 test.vhdl -e
+
+clean
-- 
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