diff options
| -rw-r--r-- | pyGHDL/libghdl/std_names.py | 365 | ||||
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 2 | ||||
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 3 | ||||
| -rw-r--r-- | src/synth/netlists-cleanup.adb | 29 | ||||
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-parse.adb | 12 | ||||
| -rw-r--r-- | testsuite/synth/issue1850/detector.psl | 31 | ||||
| -rw-r--r-- | testsuite/synth/issue1850/pulse.vhdl | 43 | ||||
| -rwxr-xr-x | testsuite/synth/issue1850/testsuite.sh | 8 | ||||
| -rw-r--r-- | testsuite/synth/synth154/keep.vhdl | 48 | ||||
| -rwxr-xr-x | testsuite/synth/synth154/testsuite.sh | 10 |
13 files changed, 369 insertions, 190 deletions
diff --git a/pyGHDL/libghdl/std_names.py b/pyGHDL/libghdl/std_names.py index 7f27a0116..f1f63f12a 100644 --- a/pyGHDL/libghdl/std_names.py +++ b/pyGHDL/libghdl/std_names.py @@ -644,185 +644,186 @@ class Name: Anyseq = 847 Gclk = 848 Loc = 849 - Last_Synthesis = 849 - First_Directive = 850 - Define = 850 - Endif = 851 - Ifdef = 852 - Ifndef = 853 - Include = 854 - Timescale = 855 - Undef = 856 - Protect = 857 - Begin_Protected = 858 - End_Protected = 859 - Key_Block = 860 - Data_Block = 861 - Line = 862 - Celldefine = 863 - Endcelldefine = 864 - Default_Nettype = 865 - Resetall = 866 - Last_Directive = 866 - First_Systask = 867 - Bits = 867 - D_Root = 868 - D_Unit = 869 - Last_Systask = 869 - First_SV_Method = 870 - Size = 870 - Insert = 871 - Delete = 872 - Pop_Front = 873 - Pop_Back = 874 - Push_Front = 875 - Push_Back = 876 - Name = 877 - Len = 878 - Substr = 879 - Exists = 880 - Atoi = 881 - Itoa = 882 - Find = 883 - Find_Index = 884 - Find_First = 885 - Find_First_Index = 886 - Find_Last = 887 - Find_Last_Index = 888 - Num = 889 - Randomize = 890 - Pre_Randomize = 891 - Post_Randomize = 892 - Srandom = 893 - Get_Randstate = 894 - Set_Randstate = 895 - Seed = 896 - State = 897 - Last_SV_Method = 897 - First_BSV = 898 - uAction = 898 - uActionValue = 899 - BVI = 900 - uC = 901 - uCF = 902 - uE = 903 - uSB = 904 - uSBR = 905 - Action = 906 - Endaction = 907 - Actionvalue = 908 - Endactionvalue = 909 - Ancestor = 910 - Clocked_By = 911 - Default_Clock = 912 - Default_Reset = 913 - Dependencies = 914 - Deriving = 915 - Determines = 916 - Enable = 917 - Ifc_Inout = 918 - Input_Clock = 919 - Input_Reset = 920 - Instance = 921 - Endinstance = 922 - Let = 923 - Match = 924 - Method = 925 - Endmethod = 926 - Numeric = 927 - Output_Clock = 928 - Output_Reset = 929 - Par = 930 - Endpar = 931 - Path = 932 - Provisos = 933 - Ready = 934 - Reset_By = 935 - Rule = 936 - Endrule = 937 - Rules = 938 - Endrules = 939 - Same_Family = 940 - Schedule = 941 - Seq = 942 - Endseq = 943 - Typeclass = 944 - Endtypeclass = 945 - Valueof = 946 - uValueof = 947 - Last_BSV = 947 - First_Comment = 948 - Psl = 948 - Pragma = 949 - Synthesis = 950 - Synopsys = 951 - Translate_Off = 952 - Translate_On = 953 - Translate = 954 - Synthesis_Off = 955 - Synthesis_On = 956 - Off = 957 - Full_Case = 958 - Parallel_Case = 959 - Last_Comment = 959 - First_PSL = 960 - A = 960 - Af = 961 - Ag = 962 - Ax = 963 - Abort = 964 - Assume_Guarantee = 965 - Async_Abort = 966 - Before = 967 - Clock = 968 - E = 969 - Ef = 970 - Eg = 971 - Ex = 972 - Endpoint = 973 - Eventually = 974 - Fairness = 975 - Fell = 976 - Forall = 977 - G = 978 - Inf = 979 - Inherit = 980 - Never = 981 - Next_A = 982 - Next_E = 983 - Next_Event = 984 - Next_Event_A = 985 - Next_Event_E = 986 - Onehot = 987 - Onehot0 = 988 - Prev = 989 - Rose = 990 - Strong = 991 - Sync_Abort = 992 - W = 993 - Whilenot = 994 - Within = 995 - X = 996 - Last_PSL = 996 - First_Edif = 997 - Celltype = 1007 - View = 1008 - Viewtype = 1009 - Direction = 1010 - Contents = 1011 - Net = 1012 - Viewref = 1013 - Cellref = 1014 - Libraryref = 1015 - Portinstance = 1016 - Joined = 1017 - Portref = 1018 - Instanceref = 1019 - Design = 1020 - Designator = 1021 - Owner = 1022 - Member = 1023 - Number = 1024 - Rename = 1025 - Userdata = 1026 - Last_Edif = 1026 + Keep = 850 + Last_Synthesis = 850 + First_Directive = 851 + Define = 851 + Endif = 852 + Ifdef = 853 + Ifndef = 854 + Include = 855 + Timescale = 856 + Undef = 857 + Protect = 858 + Begin_Protected = 859 + End_Protected = 860 + Key_Block = 861 + Data_Block = 862 + Line = 863 + Celldefine = 864 + Endcelldefine = 865 + Default_Nettype = 866 + Resetall = 867 + Last_Directive = 867 + First_Systask = 868 + Bits = 868 + D_Root = 869 + D_Unit = 870 + Last_Systask = 870 + First_SV_Method = 871 + Size = 871 + Insert = 872 + Delete = 873 + Pop_Front = 874 + Pop_Back = 875 + Push_Front = 876 + Push_Back = 877 + Name = 878 + Len = 879 + Substr = 880 + Exists = 881 + Atoi = 882 + Itoa = 883 + Find = 884 + Find_Index = 885 + Find_First = 886 + Find_First_Index = 887 + Find_Last = 888 + Find_Last_Index = 889 + Num = 890 + Randomize = 891 + Pre_Randomize = 892 + Post_Randomize = 893 + Srandom = 894 + Get_Randstate = 895 + Set_Randstate = 896 + Seed = 897 + State = 898 + Last_SV_Method = 898 + First_BSV = 899 + uAction = 899 + uActionValue = 900 + BVI = 901 + uC = 902 + uCF = 903 + uE = 904 + uSB = 905 + uSBR = 906 + Action = 907 + Endaction = 908 + Actionvalue = 909 + Endactionvalue = 910 + Ancestor = 911 + Clocked_By = 912 + Default_Clock = 913 + Default_Reset = 914 + Dependencies = 915 + Deriving = 916 + Determines = 917 + Enable = 918 + Ifc_Inout = 919 + Input_Clock = 920 + Input_Reset = 921 + Instance = 922 + Endinstance = 923 + Let = 924 + Match = 925 + Method = 926 + Endmethod = 927 + Numeric = 928 + Output_Clock = 929 + Output_Reset = 930 + Par = 931 + Endpar = 932 + Path = 933 + Provisos = 934 + Ready = 935 + Reset_By = 936 + Rule = 937 + Endrule = 938 + Rules = 939 + Endrules = 940 + Same_Family = 941 + Schedule = 942 + Seq = 943 + Endseq = 944 + Typeclass = 945 + Endtypeclass = 946 + Valueof = 947 + uValueof = 948 + Last_BSV = 948 + First_Comment = 949 + Psl = 949 + Pragma = 950 + Synthesis = 951 + Synopsys = 952 + Translate_Off = 953 + Translate_On = 954 + Translate = 955 + Synthesis_Off = 956 + Synthesis_On = 957 + Off = 958 + Full_Case = 959 + Parallel_Case = 960 + Last_Comment = 960 + First_PSL = 961 + A = 961 + Af = 962 + Ag = 963 + Ax = 964 + Abort = 965 + Assume_Guarantee = 966 + Async_Abort = 967 + Before = 968 + Clock = 969 + E = 970 + Ef = 971 + Eg = 972 + Ex = 973 + Endpoint = 974 + Eventually = 975 + Fairness = 976 + Fell = 977 + Forall = 978 + G = 979 + Inf = 980 + Inherit = 981 + Never = 982 + Next_A = 983 + Next_E = 984 + Next_Event = 985 + Next_Event_A = 986 + Next_Event_E = 987 + Onehot = 988 + Onehot0 = 989 + Prev = 990 + Rose = 991 + Strong = 992 + Sync_Abort = 993 + W = 994 + Whilenot = 995 + Within = 996 + X = 997 + Last_PSL = 997 + First_Edif = 998 + Celltype = 1008 + View = 1009 + Viewtype = 1010 + Direction = 1011 + Contents = 1012 + Net = 1013 + Viewref = 1014 + Cellref = 1015 + Libraryref = 1016 + Portinstance = 1017 + Joined = 1018 + Portref = 1019 + Instanceref = 1020 + Design = 1021 + Designator = 1022 + Owner = 1023 + Member = 1024 + Number = 1025 + Rename = 1026 + Userdata = 1027 + Last_Edif = 1027 diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 5d76355aa..2bff76e04 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -124,7 +124,7 @@ package body Ghdlsynth is P (" -gNAME=VALUE"); P (" Override the generic NAME of the top unit"); P (" --vendor-library=NAME"); - P (" Any unit from library NAME is a black boxe"); + P (" Any unit from library NAME is a black box"); P (" --no-formal"); P (" Neither synthesize assert nor PSL"); P (" --no-assert-cover"); diff --git a/src/std_names.adb b/src/std_names.adb index ffbfce1ef..ceabfec97 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -685,6 +685,7 @@ package body Std_Names is Def ("anyseq", Name_Anyseq); Def ("gclk", Name_Gclk); Def ("loc", Name_Loc); + Def ("keep", Name_Keep); -- Verilog directives Def ("define", Name_Define); diff --git a/src/std_names.ads b/src/std_names.ads index 45558cb48..4022a7493 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -770,7 +770,8 @@ package Std_Names is Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003; Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; Name_Loc : constant Name_Id := Name_First_Synthesis + 005; - Name_Last_Synthesis : constant Name_Id := Name_Loc; + Name_Keep : constant Name_Id := Name_First_Synthesis + 006; + Name_Last_Synthesis : constant Name_Id := Name_Keep; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; diff --git a/src/synth/netlists-cleanup.adb b/src/synth/netlists-cleanup.adb index d7d74b83d..8436793a8 100644 --- a/src/synth/netlists-cleanup.adb +++ b/src/synth/netlists-cleanup.adb @@ -16,6 +16,8 @@ -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <gnu.org/licenses>. +with Std_Names; + with Netlists.Utils; use Netlists.Utils; with Netlists.Gates; @@ -169,6 +171,28 @@ package body Netlists.Cleanup is end loop; end Remove_Output_Gates; + function Has_Keep (Inst : Instance) return Boolean + is + Attr : Attribute; + Val : Pval; + begin + if not Has_Attribute (Inst) then + return False; + end if; + + Attr := Get_First_Attribute (Inst); + while Attr /= No_Attribute loop + if Get_Attribute_Name (Attr) = Std_Names.Name_Keep then + Val := Get_Attribute_Pval (Attr); + pragma Assert (Get_Pval_Length (Val) = 1); + return Read_Pval (Val, 0) = (1, 0); + end if; + Attr := Get_Attribute_Next (Attr); + end loop; + + return False; + end Has_Keep; + procedure Insert_Mark_And_Sweep (Inspect : in out Instance_Tables.Instance; Inst : Instance) is begin @@ -205,6 +229,11 @@ package body Netlists.Cleanup is | Id_User_Parameters => -- Always keep user modules. Insert_Mark_And_Sweep (Inspect, Inst); + when Id_Signal + | Id_Isignal => + if Has_Keep (Inst) then + Insert_Mark_And_Sweep (Inspect, Inst); + end if; when others => null; end case; diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 26c511480..28d473a89 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -236,9 +236,7 @@ package body Netlists.Disp_Verilog is I : Input; begin I := Get_First_Sink (O); - if I = No_Input then - Put ("open"); - else + if I /= No_Input then Disp_Net_Name (O); end if; end; diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 2634af688..bfa3db4be 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3749,7 +3749,8 @@ package body Synth.Vhdl_Stmts is Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyconst); when Name_Anyseq => Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyseq); - when Name_Loc => + when Name_Loc + | Name_Keep => -- Applies to nets/ports. null; when others => diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 01c8df6ca..6a6f67024 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -5457,7 +5457,8 @@ package body Vhdl.Parse is | Iir_Kind_Package_Body | Iir_Kind_Protected_Type_Body | Iir_Kind_Protected_Type_Declaration - | Iir_Kind_Simultaneous_Procedural_Statement => + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Vunit_Declaration => Error_Msg_Parse ("configuration specification not allowed here"); when Iir_Kind_Architecture_Body @@ -11301,7 +11302,6 @@ package body Vhdl.Parse is | Tok_Impure | Tok_Procedure | Tok_Alias - | Tok_For | Tok_Attribute | Tok_Disconnect | Tok_Use @@ -11318,6 +11318,14 @@ package body Vhdl.Parse is Vhdl.Scanner.Flag_Psl := False; Item := Parse_Declaration (Res, Res); + when Tok_For => + Vhdl.Scanner.Flag_Psl := False; + if Label = Null_Identifier then + Item := Parse_Declaration (Res, Res); + else + Item := Parse_Concurrent_Statement (Res, Label); + end if; + when Tok_End | Tok_Eof | Tok_Right_Curly => diff --git a/testsuite/synth/issue1850/detector.psl b/testsuite/synth/issue1850/detector.psl new file mode 100644 index 000000000..656c2d659 --- /dev/null +++ b/testsuite/synth/issue1850/detector.psl @@ -0,0 +1,31 @@ +vunit i_rising_pulse_detector(rising_pulse_detector(rising_pulse_detector_1)) +{ + + default clock is rising_edge(clk); + + -- reset is true at beginning + f_reset_initial : assume {rst}; + -- no reset after begining + f_reset_disable : assume always {not rst} |=> {not rst}; + + + --working cover without generate + fc_output_4 : cover {output_pulse(4) = '1'}; + + -- generate cover pulse + g1: for I in 0 to 15 generate + cover {output_pulse(I) = '1'}; + end generate; + + --working bmc witout generate: + f_ouptut_7 : assert always {(not rst) and output_pulse(7) = '1'} + |=> {output_pulse(7) = '0'}; + + -- generate pulse one cycle assertion + g2: for J in 0 to 15 generate + assert always {(not rst) and output_pulse(J) = '1'} |=> {output_pulse(J) = '0'}; + end generate; + + +} -- vunit i_rising_pulse_detector(rising_pulse_detector(rising_pulse_detector_1)) + diff --git a/testsuite/synth/issue1850/pulse.vhdl b/testsuite/synth/issue1850/pulse.vhdl new file mode 100644 index 000000000..97f4dd893 --- /dev/null +++ b/testsuite/synth/issue1850/pulse.vhdl @@ -0,0 +1,43 @@ +-- Created on : 11/08/2021 +-- Author : Fabien Marteau <fabien.marteau@armadeus.com> +-- Copyright (c) ARMadeus systems 2015 + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + + +Entity rising_pulse_detector is +generic( WAITPRETRIGG_CNT: natural := 1000); +port +( + clk : in std_logic; + rst : in std_logic; + + inputvec : in std_logic_vector(15 downto 0); + + output_pulse : out std_logic_vector(15 downto 0) + +); +end entity; + +Architecture rising_pulse_detector_1 of rising_pulse_detector is + + signal inputvec_old, inputvec_pulse : std_logic_vector(15 downto 0); + +begin + + output_pulse <= inputvec_pulse; + + process(clk, rst) + begin + if(rst = '1') then + inputvec_old <= (others => '0'); + inputvec_pulse <= (others => '0'); + elsif(rising_edge(clk)) then + inputvec_pulse <= (not inputvec_old) and inputvec; + inputvec_old <= inputvec; + end if; + end process; + +end architecture rising_pulse_detector_1; diff --git a/testsuite/synth/issue1850/testsuite.sh b/testsuite/synth/issue1850/testsuite.sh new file mode 100755 index 000000000..81eec2fc2 --- /dev/null +++ b/testsuite/synth/issue1850/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth pulse.vhdl detector.psl -e > syn_pulse.vhdl + +echo "Test successful" diff --git a/testsuite/synth/synth154/keep.vhdl b/testsuite/synth/synth154/keep.vhdl new file mode 100644 index 000000000..e8bb69132 --- /dev/null +++ b/testsuite/synth/synth154/keep.vhdl @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity leds is + port (clk : in std_logic; + led1, led2, led3, led4, led5 : out std_logic); +end leds; + +architecture blink of leds is + + signal clk_4hz: std_logic := '0'; + constant gates: integer := 3 - 1; + signal max: integer := 3e6; + signal A: std_logic_vector(0 to gates) := ( others => '0'); + + attribute keep: boolean; + attribute keep of A: signal is true; + + signal B: std_logic := '1'; + signal C: std_logic := '1'; + signal val: std_logic := '0'; + signal data: std_logic := '0'; + +begin + process (clk) + variable counter : unsigned (23 downto 0) := (others => '0'); + begin + if rising_edge(clk) then + if counter >= max then + counter := x"000000"; + clk_4hz <= not clk_4hz; + else + counter := counter + 1; + end if; + end if; + end process; + +GEN: + for i in 0 to gates generate + A(i) <= not A(gates - i); + end generate GEN; + + led2 <= clk_4hz; + led3 <= clk_4hz; + led4 <= clk_4hz; + led5 <= clk_4hz; +end; diff --git a/testsuite/synth/synth154/testsuite.sh b/testsuite/synth/synth154/testsuite.sh new file mode 100755 index 000000000..00c001dcb --- /dev/null +++ b/testsuite/synth/synth154/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_analyze keep +grep -q "signal a : " syn_keep.vhdl +clean + +echo "Test successful" |