4 files changed, 119 insertions, 0 deletions
diff --git a/testsuite/synth/issue1681/repro2.vhdl b/testsuite/synth/issue1681/repro2.vhdl
new file mode 100644
index 000000000..aedf04ad6
--- /dev/null
+++ b/testsuite/synth/issue1681/repro2.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+  generic(
+    clock_count_c    : natural range 1 to 2 := 2
+    );
+  port(
+    reset_n_i : in  std_ulogic;
+    clock_i   : in  std_ulogic_vector(0 to clock_count_c-1)
+    );
+
+end ;
+
+architecture beh of repro2 is
+
+  type regs_t is
+  record
+    foo: std_ulogic;
+  end record;
+
+  signal r, rin: regs_t;
+  
+begin
+
+  regs: process (clock_i, reset_n_i)
+  begin
+    if clock_i(clock_count_c-1)'event and clock_i(0) = '1' then
+      if reset_n_i = '0' then
+        r.foo <= '0';
+      else
+        r <= rin;
+      end if;
+    end if;
+  end process;
+  
+end architecture;
diff --git a/testsuite/synth/issue1681/repro3.vhdl b/testsuite/synth/issue1681/repro3.vhdl
new file mode 100644
index 000000000..b93cb9609
--- /dev/null
+++ b/testsuite/synth/issue1681/repro3.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3 is
+  generic(
+    clock_count_c    : natural range 1 to 2 := 2
+    );
+  port(
+    reset_n_i : in  std_ulogic;
+    clock_i   : in  std_ulogic_vector(0 to clock_count_c-1)
+    );
+
+end ;
+
+architecture beh of repro3 is
+
+  type regs_t is
+  record
+    foo: std_ulogic;
+  end record;
+
+  signal r, rin: regs_t;
+  
+begin
+
+  regs: process (clock_i, reset_n_i)
+  begin
+    if clock_i(clock_count_c-1)'event and clock_i(1) = '1' then
+      if reset_n_i = '0' then
+        r.foo <= '0';
+      else
+        r <= rin;
+      end if;
+    end if;
+  end process;
+  
+end architecture;
diff --git a/testsuite/synth/issue1681/test_fail.vhdl b/testsuite/synth/issue1681/test_fail.vhdl
new file mode 100644
index 000000000..fc3301021
--- /dev/null
+++ b/testsuite/synth/issue1681/test_fail.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_fail is
+  generic(
+    clock_count_c    : natural range 1 to 2 := 2
+    );
+  port(
+    reset_n_i : in  std_ulogic;
+    clock_i   : in  std_ulogic_vector(0 to clock_count_c-1)
+    );
+
+end test_fail;
+
+architecture beh of test_fail is
+
+  type regs_t is
+  record
+    foo: std_ulogic;
+  end record;
+
+  signal r, rin: regs_t;
+  
+begin
+
+  regs: process (clock_i, reset_n_i)
+  begin
+    if clock_i(clock_count_c-1)'event and clock_i(clock_count_c-1) = '1' then
+      if reset_n_i = '0' then
+        r.foo <= '0';
+      else
+        r <= rin;
+      end if;
+    end if;
+  end process;
+  
+end architecture;
diff --git a/testsuite/synth/issue1681/testsuite.sh b/testsuite/synth/issue1681/testsuite.sh
new file mode 100755
index 000000000..d4f3b384e
--- /dev/null
+++ b/testsuite/synth/issue1681/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only test_fail
+synth_only repro3
+
+echo "Test successful"