2 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/gna/issue1867/repro.vhdl b/testsuite/gna/issue1867/repro.vhdl
new file mode 100644
index 000000000..999691c5f
--- /dev/null
+++ b/testsuite/gna/issue1867/repro.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity one is
+    generic (
+        PORT_WIDTH : integer
+    );
+    port (
+        INPUT : in std_logic_vector(PORT_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture rtl of one is
+begin
+end architecture;
+
+-----------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity two is
+end entity;
+
+architecture rtl of two is
+    signal ctr : integer range 0 to 7;
+begin
+    one_inst : entity work.one
+    generic map (
+        PORT_WIDTH => 3
+    )
+    port map (
+        INPUT => to_slv(ctr, 3)
+    );
+end architecture;
diff --git a/testsuite/gna/issue1867/testsuite.sh b/testsuite/gna/issue1867/testsuite.sh
new file mode 100755
index 000000000..2da92c768
--- /dev/null
+++ b/testsuite/gna/issue1867/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate two
+
+clean
+
+echo "Test successful"