diff options
-rw-r--r-- | python/libghdl/thin/std_names.py | 352 | ||||
-rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 389 | ||||
-rw-r--r-- | src/vhdl/translate/trans-chap4.adb | 9 | ||||
-rw-r--r-- | src/vhdl/translate/trans-chap5.adb | 8 | ||||
-rw-r--r-- | src/vhdl/translate/trans-chap6.adb | 12 | ||||
-rw-r--r-- | src/vhdl/translate/trans-chap7.adb | 1 | ||||
-rw-r--r-- | src/vhdl/translate/trans-rtis.adb | 9 | ||||
-rw-r--r-- | src/vhdl/vhdl-canon.adb | 74 | ||||
-rw-r--r-- | src/vhdl/vhdl-elocations.adb | 1 | ||||
-rw-r--r-- | src/vhdl/vhdl-elocations.ads | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-errors.adb | 3 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.adb | 1 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 26 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes_meta.adb | 324 | ||||
-rw-r--r-- | src/vhdl/vhdl-prints.adb | 13 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem.adb | 45 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_decls.adb | 19 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_decls.ads | 14 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_names.adb | 4 | ||||
-rw-r--r-- | src/vhdl/vhdl-utils.adb | 5 |
20 files changed, 785 insertions, 526 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index bef6eee48..9098c9db4 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -572,176 +572,182 @@ class Name: Std_Logic_Signed = 786 Std_Logic_Textio = 787 Std_Logic_Unsigned = 788 - Last_Ieee = 788 - First_Directive = 789 - Define = 789 - Endif = 790 - Ifdef = 791 - Ifndef = 792 - Include = 793 - Timescale = 794 - Undef = 795 - Protect = 796 - Begin_Protected = 797 - End_Protected = 798 - Key_Block = 799 - Data_Block = 800 - Line = 801 - Celldefine = 802 - Endcelldefine = 803 - Default_Nettype = 804 - Resetall = 805 - Last_Directive = 805 - First_Systask = 806 - Bits = 806 - D_Root = 807 - D_Unit = 808 - Last_Systask = 808 - First_SV_Method = 809 - Size = 809 - Insert = 810 - Delete = 811 - Pop_Front = 812 - Pop_Back = 813 - Push_Front = 814 - Push_Back = 815 - Name = 816 - Len = 817 - Substr = 818 - Exists = 819 - Atoi = 820 - Itoa = 821 - Find = 822 - Find_Index = 823 - Find_First = 824 - Find_First_Index = 825 - Find_Last = 826 - Find_Last_Index = 827 - Num = 828 - Randomize = 829 - Pre_Randomize = 830 - Post_Randomize = 831 - Srandom = 832 - Get_Randstate = 833 - Set_Randstate = 834 - Seed = 835 - State = 836 - Last_SV_Method = 836 - First_BSV = 837 - uAction = 837 - uActionValue = 838 - BVI = 839 - uC = 840 - uCF = 841 - uE = 842 - uSB = 843 - uSBR = 844 - Action = 845 - Endaction = 846 - Actionvalue = 847 - Endactionvalue = 848 - Ancestor = 849 - Clocked_By = 850 - Default_Clock = 851 - Default_Reset = 852 - Dependencies = 853 - Deriving = 854 - Determines = 855 - Enable = 856 - Ifc_Inout = 857 - Input_Clock = 858 - Input_Reset = 859 - Instance = 860 - Endinstance = 861 - Let = 862 - Match = 863 - Method = 864 - Endmethod = 865 - Numeric = 866 - Output_Clock = 867 - Output_Reset = 868 - Par = 869 - Endpar = 870 - Path = 871 - Provisos = 872 - Ready = 873 - Reset_By = 874 - Rule = 875 - Endrule = 876 - Rules = 877 - Endrules = 878 - Same_Family = 879 - Schedule = 880 - Seq = 881 - Endseq = 882 - Typeclass = 883 - Endtypeclass = 884 - Valueof = 885 - uValueof = 886 - Last_BSV = 886 - First_Comment = 887 - Psl = 887 - Pragma = 888 - Last_Comment = 888 - First_PSL = 889 - A = 889 - Af = 890 - Ag = 891 - Ax = 892 - Abort = 893 - Assume_Guarantee = 894 - Before = 895 - Clock = 896 - E = 897 - Ef = 898 - Eg = 899 - Ex = 900 - Endpoint = 901 - Eventually = 902 - Fairness = 903 - Fell = 904 - Forall = 905 - G = 906 - Inf = 907 - Inherit = 908 - Never = 909 - Next_A = 910 - Next_E = 911 - Next_Event = 912 - Next_Event_A = 913 - Next_Event_E = 914 - Prev = 915 - Restrict = 916 - Restrict_Guarantee = 917 - Rose = 918 - Strong = 919 - Vmode = 920 - Vprop = 921 - Vunit = 922 - W = 923 - Whilenot = 924 - Within = 925 - X = 926 - Last_PSL = 926 - First_Edif = 927 - Celltype = 937 - View = 938 - Viewtype = 939 - Direction = 940 - Contents = 941 - Net = 942 - Viewref = 943 - Cellref = 944 - Libraryref = 945 - Portinstance = 946 - Joined = 947 - Portref = 948 - Instanceref = 949 - Design = 950 - Designator = 951 - Owner = 952 - Member = 953 - Number = 954 - Rename = 955 - Userdata = 956 - Last_Edif = 956 + To_Integer = 789 + To_Unsigned = 790 + To_Signed = 791 + Math_Real = 792 + Ceil = 793 + Log2 = 794 + Last_Ieee = 794 + First_Directive = 795 + Define = 795 + Endif = 796 + Ifdef = 797 + Ifndef = 798 + Include = 799 + Timescale = 800 + Undef = 801 + Protect = 802 + Begin_Protected = 803 + End_Protected = 804 + Key_Block = 805 + Data_Block = 806 + Line = 807 + Celldefine = 808 + Endcelldefine = 809 + Default_Nettype = 810 + Resetall = 811 + Last_Directive = 811 + First_Systask = 812 + Bits = 812 + D_Root = 813 + D_Unit = 814 + Last_Systask = 814 + First_SV_Method = 815 + Size = 815 + Insert = 816 + Delete = 817 + Pop_Front = 818 + Pop_Back = 819 + Push_Front = 820 + Push_Back = 821 + Name = 822 + Len = 823 + Substr = 824 + Exists = 825 + Atoi = 826 + Itoa = 827 + Find = 828 + Find_Index = 829 + Find_First = 830 + Find_First_Index = 831 + Find_Last = 832 + Find_Last_Index = 833 + Num = 834 + Randomize = 835 + Pre_Randomize = 836 + Post_Randomize = 837 + Srandom = 838 + Get_Randstate = 839 + Set_Randstate = 840 + Seed = 841 + State = 842 + Last_SV_Method = 842 + First_BSV = 843 + uAction = 843 + uActionValue = 844 + BVI = 845 + uC = 846 + uCF = 847 + uE = 848 + uSB = 849 + uSBR = 850 + Action = 851 + Endaction = 852 + Actionvalue = 853 + Endactionvalue = 854 + Ancestor = 855 + Clocked_By = 856 + Default_Clock = 857 + Default_Reset = 858 + Dependencies = 859 + Deriving = 860 + Determines = 861 + Enable = 862 + Ifc_Inout = 863 + Input_Clock = 864 + Input_Reset = 865 + Instance = 866 + Endinstance = 867 + Let = 868 + Match = 869 + Method = 870 + Endmethod = 871 + Numeric = 872 + Output_Clock = 873 + Output_Reset = 874 + Par = 875 + Endpar = 876 + Path = 877 + Provisos = 878 + Ready = 879 + Reset_By = 880 + Rule = 881 + Endrule = 882 + Rules = 883 + Endrules = 884 + Same_Family = 885 + Schedule = 886 + Seq = 887 + Endseq = 888 + Typeclass = 889 + Endtypeclass = 890 + Valueof = 891 + uValueof = 892 + Last_BSV = 892 + First_Comment = 893 + Psl = 893 + Pragma = 894 + Last_Comment = 894 + First_PSL = 895 + A = 895 + Af = 896 + Ag = 897 + Ax = 898 + Abort = 899 + Assume_Guarantee = 900 + Before = 901 + Clock = 902 + E = 903 + Ef = 904 + Eg = 905 + Ex = 906 + Endpoint = 907 + Eventually = 908 + Fairness = 909 + Fell = 910 + Forall = 911 + G = 912 + Inf = 913 + Inherit = 914 + Never = 915 + Next_A = 916 + Next_E = 917 + Next_Event = 918 + Next_Event_A = 919 + Next_Event_E = 920 + Prev = 921 + Restrict = 922 + Restrict_Guarantee = 923 + Rose = 924 + Strong = 925 + Vmode = 926 + Vprop = 927 + Vunit = 928 + W = 929 + Whilenot = 930 + Within = 931 + X = 932 + Last_PSL = 932 + First_Edif = 933 + Celltype = 943 + View = 944 + Viewtype = 945 + Direction = 946 + Contents = 947 + Net = 948 + Viewref = 949 + Cellref = 950 + Libraryref = 951 + Portinstance = 952 + Joined = 953 + Portref = 954 + Instanceref = 955 + Design = 956 + Designator = 957 + Owner = 958 + Member = 959 + Number = 960 + Rename = 961 + Userdata = 962 + Last_Edif = 962 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 61ff4d14e..62aac4a98 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -132,155 +132,156 @@ class Iir_Kind: Interface_Package_Declaration = 117 Interface_Function_Declaration = 118 Interface_Procedure_Declaration = 119 - Signal_Attribute_Declaration = 120 - Identity_Operator = 121 - Negation_Operator = 122 - Absolute_Operator = 123 - Not_Operator = 124 - Implicit_Condition_Operator = 125 - Condition_Operator = 126 - Reduction_And_Operator = 127 - Reduction_Or_Operator = 128 - Reduction_Nand_Operator = 129 - Reduction_Nor_Operator = 130 - Reduction_Xor_Operator = 131 - Reduction_Xnor_Operator = 132 - And_Operator = 133 - Or_Operator = 134 - Nand_Operator = 135 - Nor_Operator = 136 - Xor_Operator = 137 - Xnor_Operator = 138 - Equality_Operator = 139 - Inequality_Operator = 140 - Less_Than_Operator = 141 - Less_Than_Or_Equal_Operator = 142 - Greater_Than_Operator = 143 - Greater_Than_Or_Equal_Operator = 144 - Match_Equality_Operator = 145 - Match_Inequality_Operator = 146 - Match_Less_Than_Operator = 147 - Match_Less_Than_Or_Equal_Operator = 148 - Match_Greater_Than_Operator = 149 - Match_Greater_Than_Or_Equal_Operator = 150 - Sll_Operator = 151 - Sla_Operator = 152 - Srl_Operator = 153 - Sra_Operator = 154 - Rol_Operator = 155 - Ror_Operator = 156 - Addition_Operator = 157 - Substraction_Operator = 158 - Concatenation_Operator = 159 - Multiplication_Operator = 160 - Division_Operator = 161 - Modulus_Operator = 162 - Remainder_Operator = 163 - Exponentiation_Operator = 164 - Function_Call = 165 - Aggregate = 166 - Parenthesis_Expression = 167 - Qualified_Expression = 168 - Type_Conversion = 169 - Allocator_By_Expression = 170 - Allocator_By_Subtype = 171 - Selected_Element = 172 - Dereference = 173 - Implicit_Dereference = 174 - Slice_Name = 175 - Indexed_Name = 176 - Psl_Expression = 177 - Sensitized_Process_Statement = 178 - Process_Statement = 179 - Concurrent_Simple_Signal_Assignment = 180 - Concurrent_Conditional_Signal_Assignment = 181 - Concurrent_Selected_Signal_Assignment = 182 - Concurrent_Assertion_Statement = 183 - Concurrent_Procedure_Call_Statement = 184 - Psl_Assert_Statement = 185 - Psl_Cover_Statement = 186 - Block_Statement = 187 - If_Generate_Statement = 188 - Case_Generate_Statement = 189 - For_Generate_Statement = 190 - Component_Instantiation_Statement = 191 - Psl_Default_Clock = 192 - Simple_Simultaneous_Statement = 193 - Generate_Statement_Body = 194 - If_Generate_Else_Clause = 195 - Simple_Signal_Assignment_Statement = 196 - Conditional_Signal_Assignment_Statement = 197 - Selected_Waveform_Assignment_Statement = 198 - Null_Statement = 199 - Assertion_Statement = 200 - Report_Statement = 201 - Wait_Statement = 202 - Variable_Assignment_Statement = 203 - Conditional_Variable_Assignment_Statement = 204 - Return_Statement = 205 - For_Loop_Statement = 206 - While_Loop_Statement = 207 - Next_Statement = 208 - Exit_Statement = 209 - Case_Statement = 210 - Procedure_Call_Statement = 211 - If_Statement = 212 - Elsif = 213 - Character_Literal = 214 - Simple_Name = 215 - Selected_Name = 216 - Operator_Symbol = 217 - Reference_Name = 218 - External_Constant_Name = 219 - External_Signal_Name = 220 - External_Variable_Name = 221 - Selected_By_All_Name = 222 - Parenthesis_Name = 223 - Package_Pathname = 224 - Absolute_Pathname = 225 - Relative_Pathname = 226 - Pathname_Element = 227 - Base_Attribute = 228 - Subtype_Attribute = 229 - Element_Attribute = 230 - Left_Type_Attribute = 231 - Right_Type_Attribute = 232 - High_Type_Attribute = 233 - Low_Type_Attribute = 234 - Ascending_Type_Attribute = 235 - Image_Attribute = 236 - Value_Attribute = 237 - Pos_Attribute = 238 - Val_Attribute = 239 - Succ_Attribute = 240 - Pred_Attribute = 241 - Leftof_Attribute = 242 - Rightof_Attribute = 243 - Delayed_Attribute = 244 - Stable_Attribute = 245 - Quiet_Attribute = 246 - Transaction_Attribute = 247 - Event_Attribute = 248 - Active_Attribute = 249 - Last_Event_Attribute = 250 - Last_Active_Attribute = 251 - Last_Value_Attribute = 252 - Driving_Attribute = 253 - Driving_Value_Attribute = 254 - Behavior_Attribute = 255 - Structure_Attribute = 256 - Simple_Name_Attribute = 257 - Instance_Name_Attribute = 258 - Path_Name_Attribute = 259 - Left_Array_Attribute = 260 - Right_Array_Attribute = 261 - High_Array_Attribute = 262 - Low_Array_Attribute = 263 - Length_Array_Attribute = 264 - Ascending_Array_Attribute = 265 - Range_Array_Attribute = 266 - Reverse_Range_Array_Attribute = 267 - Attribute_Name = 268 + Anonymous_Signal_Declaration = 120 + Signal_Attribute_Declaration = 121 + Identity_Operator = 122 + Negation_Operator = 123 + Absolute_Operator = 124 + Not_Operator = 125 + Implicit_Condition_Operator = 126 + Condition_Operator = 127 + Reduction_And_Operator = 128 + Reduction_Or_Operator = 129 + Reduction_Nand_Operator = 130 + Reduction_Nor_Operator = 131 + Reduction_Xor_Operator = 132 + Reduction_Xnor_Operator = 133 + And_Operator = 134 + Or_Operator = 135 + Nand_Operator = 136 + Nor_Operator = 137 + Xor_Operator = 138 + Xnor_Operator = 139 + Equality_Operator = 140 + Inequality_Operator = 141 + Less_Than_Operator = 142 + Less_Than_Or_Equal_Operator = 143 + Greater_Than_Operator = 144 + Greater_Than_Or_Equal_Operator = 145 + Match_Equality_Operator = 146 + Match_Inequality_Operator = 147 + Match_Less_Than_Operator = 148 + Match_Less_Than_Or_Equal_Operator = 149 + Match_Greater_Than_Operator = 150 + Match_Greater_Than_Or_Equal_Operator = 151 + Sll_Operator = 152 + Sla_Operator = 153 + Srl_Operator = 154 + Sra_Operator = 155 + Rol_Operator = 156 + Ror_Operator = 157 + Addition_Operator = 158 + Substraction_Operator = 159 + Concatenation_Operator = 160 + Multiplication_Operator = 161 + Division_Operator = 162 + Modulus_Operator = 163 + Remainder_Operator = 164 + Exponentiation_Operator = 165 + Function_Call = 166 + Aggregate = 167 + Parenthesis_Expression = 168 + Qualified_Expression = 169 + Type_Conversion = 170 + Allocator_By_Expression = 171 + Allocator_By_Subtype = 172 + Selected_Element = 173 + Dereference = 174 + Implicit_Dereference = 175 + Slice_Name = 176 + Indexed_Name = 177 + Psl_Expression = 178 + Sensitized_Process_Statement = 179 + Process_Statement = 180 + Concurrent_Simple_Signal_Assignment = 181 + Concurrent_Conditional_Signal_Assignment = 182 + Concurrent_Selected_Signal_Assignment = 183 + Concurrent_Assertion_Statement = 184 + Concurrent_Procedure_Call_Statement = 185 + Psl_Assert_Statement = 186 + Psl_Cover_Statement = 187 + Block_Statement = 188 + If_Generate_Statement = 189 + Case_Generate_Statement = 190 + For_Generate_Statement = 191 + Component_Instantiation_Statement = 192 + Psl_Default_Clock = 193 + Simple_Simultaneous_Statement = 194 + Generate_Statement_Body = 195 + If_Generate_Else_Clause = 196 + Simple_Signal_Assignment_Statement = 197 + Conditional_Signal_Assignment_Statement = 198 + Selected_Waveform_Assignment_Statement = 199 + Null_Statement = 200 + Assertion_Statement = 201 + Report_Statement = 202 + Wait_Statement = 203 + Variable_Assignment_Statement = 204 + Conditional_Variable_Assignment_Statement = 205 + Return_Statement = 206 + For_Loop_Statement = 207 + While_Loop_Statement = 208 + Next_Statement = 209 + Exit_Statement = 210 + Case_Statement = 211 + Procedure_Call_Statement = 212 + If_Statement = 213 + Elsif = 214 + Character_Literal = 215 + Simple_Name = 216 + Selected_Name = 217 + Operator_Symbol = 218 + Reference_Name = 219 + External_Constant_Name = 220 + External_Signal_Name = 221 + External_Variable_Name = 222 + Selected_By_All_Name = 223 + Parenthesis_Name = 224 + Package_Pathname = 225 + Absolute_Pathname = 226 + Relative_Pathname = 227 + Pathname_Element = 228 + Base_Attribute = 229 + Subtype_Attribute = 230 + Element_Attribute = 231 + Left_Type_Attribute = 232 + Right_Type_Attribute = 233 + High_Type_Attribute = 234 + Low_Type_Attribute = 235 + Ascending_Type_Attribute = 236 + Image_Attribute = 237 + Value_Attribute = 238 + Pos_Attribute = 239 + Val_Attribute = 240 + Succ_Attribute = 241 + Pred_Attribute = 242 + Leftof_Attribute = 243 + Rightof_Attribute = 244 + Delayed_Attribute = 245 + Stable_Attribute = 246 + Quiet_Attribute = 247 + Transaction_Attribute = 248 + Event_Attribute = 249 + Active_Attribute = 250 + Last_Event_Attribute = 251 + Last_Active_Attribute = 252 + Last_Value_Attribute = 253 + Driving_Attribute = 254 + Driving_Value_Attribute = 255 + Behavior_Attribute = 256 + Structure_Attribute = 257 + Simple_Name_Attribute = 258 + Instance_Name_Attribute = 259 + Path_Name_Attribute = 260 + Left_Array_Attribute = 261 + Right_Array_Attribute = 262 + High_Array_Attribute = 263 + Low_Array_Attribute = 264 + Length_Array_Attribute = 265 + Ascending_Array_Attribute = 266 + Range_Array_Attribute = 267 + Reverse_Range_Array_Attribute = 268 + Attribute_Name = 269 class Iir_Kinds: @@ -1043,24 +1044,78 @@ class Iir_Predefined: Ieee_1164_Vector_Xor = 183 Ieee_1164_Vector_Xnor = 184 Ieee_1164_Vector_Not = 185 - Ieee_Numeric_Std_Add_Uns_Uns = 186 - Ieee_Numeric_Std_Add_Uns_Nat = 187 - Ieee_Numeric_Std_Add_Nat_Uns = 188 - Ieee_Numeric_Std_Add_Sgn_Sgn = 189 - Ieee_Numeric_Std_Add_Sgn_Int = 190 - Ieee_Numeric_Std_Add_Int_Sgn = 191 - Ieee_Numeric_Std_Sub_Uns_Uns = 192 - Ieee_Numeric_Std_Sub_Uns_Nat = 193 - Ieee_Numeric_Std_Sub_Nat_Uns = 194 - Ieee_Numeric_Std_Sub_Sgn_Sgn = 195 - Ieee_Numeric_Std_Sub_Sgn_Int = 196 - Ieee_Numeric_Std_Sub_Int_Sgn = 197 - Ieee_Numeric_Std_Eq_Uns_Uns = 198 - Ieee_Numeric_Std_Eq_Uns_Nat = 199 - Ieee_Numeric_Std_Eq_Nat_Uns = 200 - Ieee_Numeric_Std_Eq_Sgn_Sgn = 201 - Ieee_Numeric_Std_Eq_Sgn_Int = 202 - Ieee_Numeric_Std_Eq_Int_Sgn = 203 + Ieee_Numeric_Std_Toint_Uns_Nat = 186 + Ieee_Numeric_Std_Toint_Sgn_Int = 187 + Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 188 + Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 189 + Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 190 + Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 191 + Ieee_Numeric_Std_Add_Uns_Uns = 192 + Ieee_Numeric_Std_Add_Uns_Nat = 193 + Ieee_Numeric_Std_Add_Nat_Uns = 194 + Ieee_Numeric_Std_Add_Sgn_Sgn = 195 + Ieee_Numeric_Std_Add_Sgn_Int = 196 + Ieee_Numeric_Std_Add_Int_Sgn = 197 + Ieee_Numeric_Std_Sub_Uns_Uns = 198 + Ieee_Numeric_Std_Sub_Uns_Nat = 199 + Ieee_Numeric_Std_Sub_Nat_Uns = 200 + Ieee_Numeric_Std_Sub_Sgn_Sgn = 201 + Ieee_Numeric_Std_Sub_Sgn_Int = 202 + Ieee_Numeric_Std_Sub_Int_Sgn = 203 + Ieee_Numeric_Std_Gt_Uns_Uns = 204 + Ieee_Numeric_Std_Gt_Uns_Nat = 205 + Ieee_Numeric_Std_Gt_Nat_Uns = 206 + Ieee_Numeric_Std_Gt_Sgn_Sgn = 207 + Ieee_Numeric_Std_Gt_Sgn_Int = 208 + Ieee_Numeric_Std_Gt_Int_Sgn = 209 + Ieee_Numeric_Std_Lt_Uns_Uns = 210 + Ieee_Numeric_Std_Lt_Uns_Nat = 211 + Ieee_Numeric_Std_Lt_Nat_Uns = 212 + Ieee_Numeric_Std_Lt_Sgn_Sgn = 213 + Ieee_Numeric_Std_Lt_Sgn_Int = 214 + Ieee_Numeric_Std_Lt_Int_Sgn = 215 + Ieee_Numeric_Std_Le_Uns_Uns = 216 + Ieee_Numeric_Std_Le_Uns_Nat = 217 + Ieee_Numeric_Std_Le_Nat_Uns = 218 + Ieee_Numeric_Std_Le_Sgn_Sgn = 219 + Ieee_Numeric_Std_Le_Sgn_Int = 220 + Ieee_Numeric_Std_Le_Int_Sgn = 221 + Ieee_Numeric_Std_Ge_Uns_Uns = 222 + Ieee_Numeric_Std_Ge_Uns_Nat = 223 + Ieee_Numeric_Std_Ge_Nat_Uns = 224 + Ieee_Numeric_Std_Ge_Sgn_Sgn = 225 + Ieee_Numeric_Std_Ge_Sgn_Int = 226 + Ieee_Numeric_Std_Ge_Int_Sgn = 227 + Ieee_Numeric_Std_Eq_Uns_Uns = 228 + Ieee_Numeric_Std_Eq_Uns_Nat = 229 + Ieee_Numeric_Std_Eq_Nat_Uns = 230 + Ieee_Numeric_Std_Eq_Sgn_Sgn = 231 + Ieee_Numeric_Std_Eq_Sgn_Int = 232 + Ieee_Numeric_Std_Eq_Int_Sgn = 233 + Ieee_Numeric_Std_Ne_Uns_Uns = 234 + Ieee_Numeric_Std_Ne_Uns_Nat = 235 + Ieee_Numeric_Std_Ne_Nat_Uns = 236 + Ieee_Numeric_Std_Ne_Sgn_Sgn = 237 + Ieee_Numeric_Std_Ne_Sgn_Int = 238 + Ieee_Numeric_Std_Ne_Int_Sgn = 239 + Ieee_Numeric_Std_Neg_Uns = 240 + Ieee_Numeric_Std_Neg_Sgn = 241 + Ieee_Math_Real_Ceil = 242 + Ieee_Math_Real_Log2 = 243 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 244 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 245 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 246 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 247 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 248 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 249 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 250 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 251 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 252 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 253 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 254 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 255 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 256 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 257 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb index 419229e66..13688263c 100644 --- a/src/vhdl/translate/trans-chap4.adb +++ b/src/vhdl/translate/trans-chap4.adb @@ -229,7 +229,8 @@ package body Trans.Chap4 is when Iir_Kind_Signal_Declaration | Iir_Kind_Interface_Signal_Declaration => Rtis.Generate_Signal_Rti (Decl); - when Iir_Kind_Guard_Signal_Declaration => + when Iir_Kind_Guard_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => -- No name created for guard signal. null; when others => @@ -1820,7 +1821,8 @@ package body Trans.Chap4 is | Iir_Kind_Constant_Declaration => Create_Object (Decl); - when Iir_Kind_Signal_Declaration => + when Iir_Kind_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => Create_Signal (Decl); when Iir_Kind_Object_Alias_Declaration => @@ -2584,7 +2586,8 @@ package body Trans.Chap4 is Need_Final := True; end if; - when Iir_Kind_Signal_Declaration => + when Iir_Kind_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => Elab_Signal_Declaration (Decl, Parent, False); when Iir_Kind_Object_Alias_Declaration => diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index 2aa7cfdea..3df3a7324 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -448,7 +448,13 @@ package body Trans.Chap5 is -- actual, but the type of the formal may be used by the actual. Set_Map_Env (Formal_Env); Chap6.Translate_Signal_Name (Formal, Formal_Sig, Formal_Val); - Actual_En := Chap7.Translate_Expression (Actual, Formal_Type); + if Get_Kind (Actual) = Iir_Kind_Reference_Name then + -- For vhdl08 association by expression. + Actual_En := Chap7.Translate_Expression + (Get_Referenced_Name (Actual), Formal_Type); + else + Actual_En := Chap7.Translate_Expression (Actual, Formal_Type); + end if; Actual_Sig := E2M (Actual_En, Get_Info (Formal_Type), Mode_Value); Mode := Connect_Value; -- raise Internal_Error; diff --git a/src/vhdl/translate/trans-chap6.adb b/src/vhdl/translate/trans-chap6.adb index a277d452b..eb757d9c7 100644 --- a/src/vhdl/translate/trans-chap6.adb +++ b/src/vhdl/translate/trans-chap6.adb @@ -1071,7 +1071,8 @@ package body Trans.Chap6 is | Iir_Kind_Quiet_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Transaction_Attribute - | Iir_Kind_Guard_Signal_Declaration => + | Iir_Kind_Guard_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => if Mode = Mode_Signal then return Get_Var (Name_Info.Signal_Sig, Type_Info, Mode_Signal); else @@ -1180,7 +1181,8 @@ package body Trans.Chap6 is | Iir_Kind_Delayed_Attribute | Iir_Kind_Transaction_Attribute | Iir_Kind_Guard_Signal_Declaration - | Iir_Kind_Object_Alias_Declaration => + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => Translate_Signal_Base (Name, Sig, Drv); when Iir_Kind_Slice_Name => declare @@ -1231,7 +1233,8 @@ package body Trans.Chap6 is begin case Get_Kind (Name) is when Iir_Kind_Signal_Declaration - | Iir_Kind_Interface_Signal_Declaration => + | Iir_Kind_Interface_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => declare Name_Type : constant Iir := Get_Type (Name); Name_Info : constant Ortho_Info_Acc := Get_Info (Name); @@ -1290,7 +1293,8 @@ package body Trans.Chap6 is | Iir_Kind_Quiet_Attribute | Iir_Kind_Delayed_Attribute | Iir_Kind_Transaction_Attribute - | Iir_Kind_Guard_Signal_Declaration => + | Iir_Kind_Guard_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => Sig := Get_Var (Name_Info.Signal_Sig, Type_Info, Mode_Signal); Val := Get_Var (Name_Info.Signal_Val, Type_Info, Mode_Value); when Iir_Kind_Interface_Signal_Declaration => diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index 3d670cf56..4d6f68fdc 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -4330,6 +4330,7 @@ package body Trans.Chap7 is | Iir_Kind_Delayed_Attribute | Iir_Kind_Transaction_Attribute | Iir_Kind_Guard_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Attribute_Value | Iir_Kind_Attribute_Name => Res := M2E (Chap6.Translate_Name (Expr, Mode_Value)); diff --git a/src/vhdl/translate/trans-rtis.adb b/src/vhdl/translate/trans-rtis.adb index 759a066cb..e59a12b92 100644 --- a/src/vhdl/translate/trans-rtis.adb +++ b/src/vhdl/translate/trans-rtis.adb @@ -1933,7 +1933,8 @@ package body Trans.Rtis is Start_Record_Aggr (List, Ghdl_Rtin_Object); Mode := 0; case Get_Kind (Decl) is - when Iir_Kind_Signal_Declaration => + when Iir_Kind_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => Comm := Ghdl_Rtik_Signal; Var := Info.Signal_Sig; when Iir_Kind_Interface_Signal_Declaration => @@ -2140,7 +2141,8 @@ package body Trans.Rtis is | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Variable_Declaration | Iir_Kind_File_Declaration - | Iir_Kind_Signal_Attribute_Declaration => + | Iir_Kind_Signal_Attribute_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => null; when Iir_Kind_Object_Alias_Declaration | Iir_Kind_Attribute_Declaration => @@ -2270,7 +2272,8 @@ package body Trans.Rtis is Add_Rti_Node (Info.Object_Rti); end; when Iir_Kind_Signal_Declaration - | Iir_Kind_Interface_Signal_Declaration => + | Iir_Kind_Interface_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => declare Info : constant Signal_Info_Acc := Get_Info (Decl); begin diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 604272813..5e1011a36 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -40,13 +40,11 @@ package body Vhdl.Canon is -- Canonicalize the chain of declarations in Declaration_Chain of -- DECL_PARENT. PARENT must be the parent of the current statements chain, -- or NULL_IIR if DECL_PARENT has no corresponding current statments. + -- TOP is used to add dependencies (from binding indications). procedure Canon_Declarations (Top : Iir_Design_Unit; Decl_Parent : Iir; Parent : Iir); - function Canon_Declaration (Top : Iir_Design_Unit; - Decl : Iir; - Parent : Iir; - Decl_Parent : Iir) + function Canon_Declaration (Top : Iir_Design_Unit; Decl : Iir; Parent : Iir) return Iir; procedure Canon_Concurrent_Stmts (Top : Iir_Design_Unit; Parent : Iir); @@ -2101,8 +2099,7 @@ package body Vhdl.Canon is Decl : constant Iir := Get_Parameter_Specification (El); New_Decl : Iir; begin - New_Decl := Canon_Declaration - (Top, Decl, Null_Iir, Null_Iir); + New_Decl := Canon_Declaration (Top, Decl, Null_Iir); pragma Assert (New_Decl = Decl); Canon_Generate_Statement_Body @@ -2245,6 +2242,7 @@ package body Vhdl.Canon is end Add_Binding_Indication_Dependence; -- Canon the component_configuration or configuration_specification CFG. + -- TOP is used to add dependences. procedure Canon_Component_Configuration (Top : Iir_Design_Unit; Cfg : Iir) is -- True iff CFG is a component_configuration. @@ -2622,7 +2620,7 @@ package body Vhdl.Canon is -- Replace ALL/OTHERS with the explicit list of signals. procedure Canon_Disconnection_Specification - (Dis : Iir_Disconnection_Specification; Decl_Parent : Iir) + (Dis : Iir_Disconnection_Specification) is Signal_List : Iir_Flist; Force : Boolean; @@ -2648,7 +2646,7 @@ package body Vhdl.Canon is Dis_Type := Get_Type (Get_Type_Mark (Dis)); N_List := Create_Iir_List; Set_Is_Ref (Dis, True); - El := Get_Declaration_Chain (Decl_Parent); + El := Get_Declaration_Chain (Get_Parent (Dis)); while El /= Null_Iir loop if Get_Kind (El) = Iir_Kind_Signal_Declaration and then Get_Type (El) = Dis_Type @@ -2739,9 +2737,8 @@ package body Vhdl.Canon is return Decl; end Canon_Package_Instantiation_Declaration; - function Canon_Declaration - (Top : Iir_Design_Unit; Decl : Iir; Parent : Iir; Decl_Parent : Iir) - return Iir + function Canon_Declaration (Top : Iir_Design_Unit; Decl : Iir; Parent : Iir) + return Iir is Stmts : Iir; begin @@ -2784,6 +2781,38 @@ package body Vhdl.Canon is Canon_Expression (Get_Default_Value (Decl)); end if; + when Iir_Kind_Anonymous_Signal_Declaration => + if Canon_Flag_Expressions then + Canon_Expression (Get_Expression (Decl)); + end if; + -- Create a signal assignment. + declare + Parent : constant Node := Get_Parent (Decl); + Asgn : Iir; + We : Iir; + Name : Iir; + begin + Asgn := Create_Iir + (Iir_Kind_Concurrent_Simple_Signal_Assignment); + Location_Copy (Asgn, Decl); + Set_Parent (Asgn, Parent); + Name := Build_Simple_Name (Decl, Decl); + Set_Type (Name, Get_Type (Decl)); + Set_Target (Asgn, Name); + Set_Delay_Mechanism (Asgn, Iir_Inertial_Delay); + + We := Create_Iir (Iir_Kind_Waveform_Element); + Location_Copy (We, Decl); + Set_We_Value (We, Get_Expression (Decl)); + Set_Expression (Decl, Null_Iir); + + Set_Waveform_Chain (Asgn, We); + + -- Prepend. + Set_Chain (Asgn, Get_Concurrent_Statement_Chain (Parent)); + Set_Concurrent_Statement_Chain (Parent, Asgn); + end; + when Iir_Kind_Iterator_Declaration => null; @@ -2803,7 +2832,7 @@ package body Vhdl.Canon is Canon_Expression (Get_Expression (Decl)); end if; when Iir_Kind_Disconnection_Specification => - Canon_Disconnection_Specification (Decl, Decl_Parent); + Canon_Disconnection_Specification (Decl); when Iir_Kind_Group_Template_Declaration => null; @@ -2856,15 +2885,34 @@ package body Vhdl.Canon is Decl : Iir; Prev_Decl : Iir; New_Decl : Iir; + Anon_Label : Natural; begin if Parent /= Null_Iir then Clear_Instantiation_Configuration (Parent, True); end if; + Anon_Label := 0; + Decl := Get_Declaration_Chain (Decl_Parent); Prev_Decl := Null_Iir; while Decl /= Null_Iir loop - New_Decl := Canon_Declaration (Top, Decl, Parent, Decl_Parent); + -- Give a name to anonymous signals. + -- Ideally it should be done in Canon_Declaration, but we need + -- a counter for all the declarations. + if Get_Kind (Decl) = Iir_Kind_Anonymous_Signal_Declaration then + declare + Str : String := "ANONYMOUS" & Natural'Image (Anon_Label); + begin + -- Note: the label starts with a capitalized + -- letter, to avoid any clash with user's + -- identifiers. + Str (10) := '_'; + Set_Identifier (Decl, Name_Table.Get_Identifier (Str)); + Anon_Label := Anon_Label + 1; + end; + end if; + + New_Decl := Canon_Declaration (Top, Decl, Parent); if New_Decl /= Decl then -- Replace declaration diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb index 8bc68245c..c08519076 100644 --- a/src/vhdl/vhdl-elocations.adb +++ b/src/vhdl/vhdl-elocations.adb @@ -282,6 +282,7 @@ package body Vhdl.Elocations is | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Signal_Attribute_Declaration | Iir_Kind_Identity_Operator | Iir_Kind_Negation_Operator diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads index fa895e111..643746527 100644 --- a/src/vhdl/vhdl-elocations.ads +++ b/src/vhdl/vhdl-elocations.ads @@ -259,6 +259,8 @@ package Vhdl.Elocations is -- Iir_Kind_Guard_Signal_Declaration (None) + -- Iir_Kind_Anonymous_Signal_Declaration (None) + -- Iir_Kind_Signal_Attribute_Declaration (None) -- Iir_Kind_Constant_Declaration (L1) diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index 1bed01213..db2f87601 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -455,6 +455,9 @@ package body Vhdl.Errors is when Iir_Kind_Signal_Attribute_Declaration => -- Should not appear. return "signal attribute"; + when Iir_Kind_Anonymous_Signal_Declaration => + -- Should not appear. + return "anonymous signal"; when Iir_Kind_Group_Template_Declaration => return Disp_Identifier (Node, "group template"); when Iir_Kind_Group_Declaration => diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index 85755105e..ae1c2bcb0 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1059,6 +1059,7 @@ package body Vhdl.Nodes is | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration | Iir_Kind_Interface_Type_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Signal_Attribute_Declaration | Iir_Kind_Identity_Operator | Iir_Kind_Negation_Operator diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index ec354499d..26d9601f8 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -1625,6 +1625,29 @@ package Vhdl.Nodes is -- -- Get/Set_Name_Staticness (State2) + -- Iir_Kind_Anonymous_Signal_Declaration (Short) + -- + -- Anonymous signal created for vhdl 2008 port association with a non + -- globally static expression. + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Identifier (Field3) + -- + -- Must be Null. + -- Get/Set_Default_Value (Field4) + -- + -- The expression that is assigned to the signal. + -- Get/Set_Expression (Field5) + -- + -- Get/Set_Type (Field1) + -- + -- Get/Set_After_Drivers_Flag (Flag5) + -- + -- Get/Set_Is_Ref (Flag12) + -- Iir_Kind_Signal_Attribute_Declaration (Short) -- -- Chain of implicit signals created from signal attribute. This is just @@ -3701,6 +3724,8 @@ package Vhdl.Nodes is -- This doesn't correspond to a name in the sources. This is an artificial -- name in the tree which is owned and reference another name. -- + -- Get/Set_Type (Field1) + -- -- Get/Set_Named_Entity (Field4) -- -- The name from which the reference was created. Can be Null_Iir if the @@ -4237,6 +4262,7 @@ package Vhdl.Nodes is Iir_Kind_Interface_Function_Declaration, -- interface Iir_Kind_Interface_Procedure_Declaration, -- interface + Iir_Kind_Anonymous_Signal_Declaration, Iir_Kind_Signal_Attribute_Declaration, -- Expressions. diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 5c55f608a..eea011a3f 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -1256,6 +1256,8 @@ package body Vhdl.Nodes_Meta is return "interface_function_declaration"; when Iir_Kind_Interface_Procedure_Declaration => return "interface_procedure_declaration"; + when Iir_Kind_Anonymous_Signal_Declaration => + return "anonymous_signal_declaration"; when Iir_Kind_Signal_Attribute_Declaration => return "signal_attribute_declaration"; when Iir_Kind_Identity_Operator => @@ -3344,6 +3346,15 @@ package body Vhdl.Nodes_Meta is Field_Chain, Field_Interface_Declaration_Chain, Field_Return_Type_Mark, + -- Iir_Kind_Anonymous_Signal_Declaration + Field_Identifier, + Field_Is_Ref, + Field_After_Drivers_Flag, + Field_Parent, + Field_Chain, + Field_Default_Value, + Field_Expression, + Field_Type, -- Iir_Kind_Signal_Attribute_Declaration Field_Parent, Field_Chain, @@ -4094,6 +4105,7 @@ package body Vhdl.Nodes_Meta is Field_Base_Name, -- Iir_Kind_Reference_Name Field_Is_Forward_Ref, + Field_Type, Field_Named_Entity, Field_Referenced_Name, -- Iir_Kind_External_Constant_Name @@ -4548,155 +4560,156 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Interface_Package_Declaration => 974, Iir_Kind_Interface_Function_Declaration => 991, Iir_Kind_Interface_Procedure_Declaration => 1004, - Iir_Kind_Signal_Attribute_Declaration => 1007, - Iir_Kind_Identity_Operator => 1011, - Iir_Kind_Negation_Operator => 1015, - Iir_Kind_Absolute_Operator => 1019, - Iir_Kind_Not_Operator => 1023, - Iir_Kind_Implicit_Condition_Operator => 1027, - Iir_Kind_Condition_Operator => 1031, - Iir_Kind_Reduction_And_Operator => 1035, - Iir_Kind_Reduction_Or_Operator => 1039, - Iir_Kind_Reduction_Nand_Operator => 1043, - Iir_Kind_Reduction_Nor_Operator => 1047, - Iir_Kind_Reduction_Xor_Operator => 1051, - Iir_Kind_Reduction_Xnor_Operator => 1055, - Iir_Kind_And_Operator => 1060, - Iir_Kind_Or_Operator => 1065, - Iir_Kind_Nand_Operator => 1070, - Iir_Kind_Nor_Operator => 1075, - Iir_Kind_Xor_Operator => 1080, - Iir_Kind_Xnor_Operator => 1085, - Iir_Kind_Equality_Operator => 1090, - Iir_Kind_Inequality_Operator => 1095, - Iir_Kind_Less_Than_Operator => 1100, - Iir_Kind_Less_Than_Or_Equal_Operator => 1105, - Iir_Kind_Greater_Than_Operator => 1110, - Iir_Kind_Greater_Than_Or_Equal_Operator => 1115, - Iir_Kind_Match_Equality_Operator => 1120, - Iir_Kind_Match_Inequality_Operator => 1125, - Iir_Kind_Match_Less_Than_Operator => 1130, - Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1135, - Iir_Kind_Match_Greater_Than_Operator => 1140, - Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1145, - Iir_Kind_Sll_Operator => 1150, - Iir_Kind_Sla_Operator => 1155, - Iir_Kind_Srl_Operator => 1160, - Iir_Kind_Sra_Operator => 1165, - Iir_Kind_Rol_Operator => 1170, - Iir_Kind_Ror_Operator => 1175, - Iir_Kind_Addition_Operator => 1180, - Iir_Kind_Substraction_Operator => 1185, - Iir_Kind_Concatenation_Operator => 1190, - Iir_Kind_Multiplication_Operator => 1195, - Iir_Kind_Division_Operator => 1200, - Iir_Kind_Modulus_Operator => 1205, - Iir_Kind_Remainder_Operator => 1210, - Iir_Kind_Exponentiation_Operator => 1215, - Iir_Kind_Function_Call => 1223, - Iir_Kind_Aggregate => 1230, - Iir_Kind_Parenthesis_Expression => 1233, - Iir_Kind_Qualified_Expression => 1237, - Iir_Kind_Type_Conversion => 1242, - Iir_Kind_Allocator_By_Expression => 1246, - Iir_Kind_Allocator_By_Subtype => 1251, - Iir_Kind_Selected_Element => 1259, - Iir_Kind_Dereference => 1264, - Iir_Kind_Implicit_Dereference => 1269, - Iir_Kind_Slice_Name => 1276, - Iir_Kind_Indexed_Name => 1282, - Iir_Kind_Psl_Expression => 1284, - Iir_Kind_Sensitized_Process_Statement => 1305, - Iir_Kind_Process_Statement => 1325, - Iir_Kind_Concurrent_Simple_Signal_Assignment => 1337, - Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1349, - Iir_Kind_Concurrent_Selected_Signal_Assignment => 1362, - Iir_Kind_Concurrent_Assertion_Statement => 1370, - Iir_Kind_Concurrent_Procedure_Call_Statement => 1377, - Iir_Kind_Psl_Assert_Statement => 1390, - Iir_Kind_Psl_Cover_Statement => 1403, - Iir_Kind_Block_Statement => 1417, - Iir_Kind_If_Generate_Statement => 1428, - Iir_Kind_Case_Generate_Statement => 1437, - Iir_Kind_For_Generate_Statement => 1446, - Iir_Kind_Component_Instantiation_Statement => 1457, - Iir_Kind_Psl_Default_Clock => 1461, - Iir_Kind_Simple_Simultaneous_Statement => 1468, - Iir_Kind_Generate_Statement_Body => 1479, - Iir_Kind_If_Generate_Else_Clause => 1485, - Iir_Kind_Simple_Signal_Assignment_Statement => 1495, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1505, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1516, - Iir_Kind_Null_Statement => 1520, - Iir_Kind_Assertion_Statement => 1527, - Iir_Kind_Report_Statement => 1533, - Iir_Kind_Wait_Statement => 1541, - Iir_Kind_Variable_Assignment_Statement => 1548, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1555, - Iir_Kind_Return_Statement => 1561, - Iir_Kind_For_Loop_Statement => 1570, - Iir_Kind_While_Loop_Statement => 1579, - Iir_Kind_Next_Statement => 1586, - Iir_Kind_Exit_Statement => 1593, - Iir_Kind_Case_Statement => 1601, - Iir_Kind_Procedure_Call_Statement => 1607, - Iir_Kind_If_Statement => 1617, - Iir_Kind_Elsif => 1623, - Iir_Kind_Character_Literal => 1631, - Iir_Kind_Simple_Name => 1639, - Iir_Kind_Selected_Name => 1648, - Iir_Kind_Operator_Symbol => 1654, - Iir_Kind_Reference_Name => 1657, - Iir_Kind_External_Constant_Name => 1665, - Iir_Kind_External_Signal_Name => 1673, - Iir_Kind_External_Variable_Name => 1682, - Iir_Kind_Selected_By_All_Name => 1688, - Iir_Kind_Parenthesis_Name => 1693, - Iir_Kind_Package_Pathname => 1697, - Iir_Kind_Absolute_Pathname => 1698, - Iir_Kind_Relative_Pathname => 1699, - Iir_Kind_Pathname_Element => 1704, - Iir_Kind_Base_Attribute => 1706, - Iir_Kind_Subtype_Attribute => 1711, - Iir_Kind_Element_Attribute => 1716, - Iir_Kind_Left_Type_Attribute => 1721, - Iir_Kind_Right_Type_Attribute => 1726, - Iir_Kind_High_Type_Attribute => 1731, - Iir_Kind_Low_Type_Attribute => 1736, - Iir_Kind_Ascending_Type_Attribute => 1741, - Iir_Kind_Image_Attribute => 1747, - Iir_Kind_Value_Attribute => 1753, - Iir_Kind_Pos_Attribute => 1759, - Iir_Kind_Val_Attribute => 1765, - Iir_Kind_Succ_Attribute => 1771, - Iir_Kind_Pred_Attribute => 1777, - Iir_Kind_Leftof_Attribute => 1783, - Iir_Kind_Rightof_Attribute => 1789, - Iir_Kind_Delayed_Attribute => 1798, - Iir_Kind_Stable_Attribute => 1807, - Iir_Kind_Quiet_Attribute => 1816, - Iir_Kind_Transaction_Attribute => 1825, - Iir_Kind_Event_Attribute => 1829, - Iir_Kind_Active_Attribute => 1833, - Iir_Kind_Last_Event_Attribute => 1837, - Iir_Kind_Last_Active_Attribute => 1841, - Iir_Kind_Last_Value_Attribute => 1845, - Iir_Kind_Driving_Attribute => 1849, - Iir_Kind_Driving_Value_Attribute => 1853, - Iir_Kind_Behavior_Attribute => 1853, - Iir_Kind_Structure_Attribute => 1853, - Iir_Kind_Simple_Name_Attribute => 1860, - Iir_Kind_Instance_Name_Attribute => 1865, - Iir_Kind_Path_Name_Attribute => 1870, - Iir_Kind_Left_Array_Attribute => 1877, - Iir_Kind_Right_Array_Attribute => 1884, - Iir_Kind_High_Array_Attribute => 1891, - Iir_Kind_Low_Array_Attribute => 1898, - Iir_Kind_Length_Array_Attribute => 1905, - Iir_Kind_Ascending_Array_Attribute => 1912, - Iir_Kind_Range_Array_Attribute => 1919, - Iir_Kind_Reverse_Range_Array_Attribute => 1926, - Iir_Kind_Attribute_Name => 1935 + Iir_Kind_Anonymous_Signal_Declaration => 1012, + Iir_Kind_Signal_Attribute_Declaration => 1015, + Iir_Kind_Identity_Operator => 1019, + Iir_Kind_Negation_Operator => 1023, + Iir_Kind_Absolute_Operator => 1027, + Iir_Kind_Not_Operator => 1031, + Iir_Kind_Implicit_Condition_Operator => 1035, + Iir_Kind_Condition_Operator => 1039, + Iir_Kind_Reduction_And_Operator => 1043, + Iir_Kind_Reduction_Or_Operator => 1047, + Iir_Kind_Reduction_Nand_Operator => 1051, + Iir_Kind_Reduction_Nor_Operator => 1055, + Iir_Kind_Reduction_Xor_Operator => 1059, + Iir_Kind_Reduction_Xnor_Operator => 1063, + Iir_Kind_And_Operator => 1068, + Iir_Kind_Or_Operator => 1073, + Iir_Kind_Nand_Operator => 1078, + Iir_Kind_Nor_Operator => 1083, + Iir_Kind_Xor_Operator => 1088, + Iir_Kind_Xnor_Operator => 1093, + Iir_Kind_Equality_Operator => 1098, + Iir_Kind_Inequality_Operator => 1103, + Iir_Kind_Less_Than_Operator => 1108, + Iir_Kind_Less_Than_Or_Equal_Operator => 1113, + Iir_Kind_Greater_Than_Operator => 1118, + Iir_Kind_Greater_Than_Or_Equal_Operator => 1123, + Iir_Kind_Match_Equality_Operator => 1128, + Iir_Kind_Match_Inequality_Operator => 1133, + Iir_Kind_Match_Less_Than_Operator => 1138, + Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1143, + Iir_Kind_Match_Greater_Than_Operator => 1148, + Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1153, + Iir_Kind_Sll_Operator => 1158, + Iir_Kind_Sla_Operator => 1163, + Iir_Kind_Srl_Operator => 1168, + Iir_Kind_Sra_Operator => 1173, + Iir_Kind_Rol_Operator => 1178, + Iir_Kind_Ror_Operator => 1183, + Iir_Kind_Addition_Operator => 1188, + Iir_Kind_Substraction_Operator => 1193, + Iir_Kind_Concatenation_Operator => 1198, + Iir_Kind_Multiplication_Operator => 1203, + Iir_Kind_Division_Operator => 1208, + Iir_Kind_Modulus_Operator => 1213, + Iir_Kind_Remainder_Operator => 1218, + Iir_Kind_Exponentiation_Operator => 1223, + Iir_Kind_Function_Call => 1231, + Iir_Kind_Aggregate => 1238, + Iir_Kind_Parenthesis_Expression => 1241, + Iir_Kind_Qualified_Expression => 1245, + Iir_Kind_Type_Conversion => 1250, + Iir_Kind_Allocator_By_Expression => 1254, + Iir_Kind_Allocator_By_Subtype => 1259, + Iir_Kind_Selected_Element => 1267, + Iir_Kind_Dereference => 1272, + Iir_Kind_Implicit_Dereference => 1277, + Iir_Kind_Slice_Name => 1284, + Iir_Kind_Indexed_Name => 1290, + Iir_Kind_Psl_Expression => 1292, + Iir_Kind_Sensitized_Process_Statement => 1313, + Iir_Kind_Process_Statement => 1333, + Iir_Kind_Concurrent_Simple_Signal_Assignment => 1345, + Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1357, + Iir_Kind_Concurrent_Selected_Signal_Assignment => 1370, + Iir_Kind_Concurrent_Assertion_Statement => 1378, + Iir_Kind_Concurrent_Procedure_Call_Statement => 1385, + Iir_Kind_Psl_Assert_Statement => 1398, + Iir_Kind_Psl_Cover_Statement => 1411, + Iir_Kind_Block_Statement => 1425, + Iir_Kind_If_Generate_Statement => 1436, + Iir_Kind_Case_Generate_Statement => 1445, + Iir_Kind_For_Generate_Statement => 1454, + Iir_Kind_Component_Instantiation_Statement => 1465, + Iir_Kind_Psl_Default_Clock => 1469, + Iir_Kind_Simple_Simultaneous_Statement => 1476, + Iir_Kind_Generate_Statement_Body => 1487, + Iir_Kind_If_Generate_Else_Clause => 1493, + Iir_Kind_Simple_Signal_Assignment_Statement => 1503, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1513, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1524, + Iir_Kind_Null_Statement => 1528, + Iir_Kind_Assertion_Statement => 1535, + Iir_Kind_Report_Statement => 1541, + Iir_Kind_Wait_Statement => 1549, + Iir_Kind_Variable_Assignment_Statement => 1556, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1563, + Iir_Kind_Return_Statement => 1569, + Iir_Kind_For_Loop_Statement => 1578, + Iir_Kind_While_Loop_Statement => 1587, + Iir_Kind_Next_Statement => 1594, + Iir_Kind_Exit_Statement => 1601, + Iir_Kind_Case_Statement => 1609, + Iir_Kind_Procedure_Call_Statement => 1615, + Iir_Kind_If_Statement => 1625, + Iir_Kind_Elsif => 1631, + Iir_Kind_Character_Literal => 1639, + Iir_Kind_Simple_Name => 1647, + Iir_Kind_Selected_Name => 1656, + Iir_Kind_Operator_Symbol => 1662, + Iir_Kind_Reference_Name => 1666, + Iir_Kind_External_Constant_Name => 1674, + Iir_Kind_External_Signal_Name => 1682, + Iir_Kind_External_Variable_Name => 1691, + Iir_Kind_Selected_By_All_Name => 1697, + Iir_Kind_Parenthesis_Name => 1702, + Iir_Kind_Package_Pathname => 1706, + Iir_Kind_Absolute_Pathname => 1707, + Iir_Kind_Relative_Pathname => 1708, + Iir_Kind_Pathname_Element => 1713, + Iir_Kind_Base_Attribute => 1715, + Iir_Kind_Subtype_Attribute => 1720, + Iir_Kind_Element_Attribute => 1725, + Iir_Kind_Left_Type_Attribute => 1730, + Iir_Kind_Right_Type_Attribute => 1735, + Iir_Kind_High_Type_Attribute => 1740, + Iir_Kind_Low_Type_Attribute => 1745, + Iir_Kind_Ascending_Type_Attribute => 1750, + Iir_Kind_Image_Attribute => 1756, + Iir_Kind_Value_Attribute => 1762, + Iir_Kind_Pos_Attribute => 1768, + Iir_Kind_Val_Attribute => 1774, + Iir_Kind_Succ_Attribute => 1780, + Iir_Kind_Pred_Attribute => 1786, + Iir_Kind_Leftof_Attribute => 1792, + Iir_Kind_Rightof_Attribute => 1798, + Iir_Kind_Delayed_Attribute => 1807, + Iir_Kind_Stable_Attribute => 1816, + Iir_Kind_Quiet_Attribute => 1825, + Iir_Kind_Transaction_Attribute => 1834, + Iir_Kind_Event_Attribute => 1838, + Iir_Kind_Active_Attribute => 1842, + Iir_Kind_Last_Event_Attribute => 1846, + Iir_Kind_Last_Active_Attribute => 1850, + Iir_Kind_Last_Value_Attribute => 1854, + Iir_Kind_Driving_Attribute => 1858, + Iir_Kind_Driving_Value_Attribute => 1862, + Iir_Kind_Behavior_Attribute => 1862, + Iir_Kind_Structure_Attribute => 1862, + Iir_Kind_Simple_Name_Attribute => 1869, + Iir_Kind_Instance_Name_Attribute => 1874, + Iir_Kind_Path_Name_Attribute => 1879, + Iir_Kind_Left_Array_Attribute => 1886, + Iir_Kind_Right_Array_Attribute => 1893, + Iir_Kind_High_Array_Attribute => 1900, + Iir_Kind_Low_Array_Attribute => 1907, + Iir_Kind_Length_Array_Attribute => 1914, + Iir_Kind_Ascending_Array_Attribute => 1921, + Iir_Kind_Range_Array_Attribute => 1928, + Iir_Kind_Reverse_Range_Array_Attribute => 1935, + Iir_Kind_Attribute_Name => 1944 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -7045,7 +7058,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => return True; when others => return False; @@ -7355,6 +7369,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Signal_Attribute_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement @@ -7466,6 +7481,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_File_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Interface_Function_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Identity_Operator | Iir_Kind_Negation_Operator | Iir_Kind_Absolute_Operator @@ -7528,6 +7544,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name | Iir_Kind_Operator_Symbol + | Iir_Kind_Reference_Name | Iir_Kind_External_Constant_Name | Iir_Kind_External_Signal_Name | Iir_Kind_External_Variable_Name @@ -7879,7 +7896,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Anonymous_Signal_Declaration => return True; when others => return False; @@ -8129,6 +8147,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Selected_Element | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement @@ -9084,6 +9103,7 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Conditional_Expression | Iir_Kind_Attribute_Specification | Iir_Kind_Disconnection_Specification + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Parenthesis_Expression | Iir_Kind_Qualified_Expression | Iir_Kind_Type_Conversion @@ -9344,6 +9364,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Package_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Signal_Attribute_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement @@ -10659,6 +10680,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_File_Declaration | Iir_Kind_Interface_Type_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index 634e2be3c..a1ce5f01b 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -2209,6 +2209,8 @@ package body Vhdl.Prints is Disp_Attribute_Specification (Ctxt, Decl); when Iir_Kind_Signal_Attribute_Declaration => null; + when Iir_Kind_Anonymous_Signal_Declaration => + null; when Iir_Kind_Group_Template_Declaration => Disp_Group_Template_Declaration (Ctxt, Decl); when Iir_Kind_Group_Declaration => @@ -3484,6 +3486,17 @@ package body Vhdl.Prints is when Iir_Kind_Implicit_Dereference => Print (Ctxt, Get_Prefix (Expr)); + when Iir_Kind_Anonymous_Signal_Declaration => + declare + Act : constant Iir := Get_Expression (Expr); + begin + if Act /= Null_Iir then + Print (Ctxt, Act); + else + Disp_Identifier (Ctxt, Expr); + end if; + end; + when Iir_Kind_Left_Type_Attribute => Disp_Name_Attribute (Ctxt, Expr, Name_Left); when Iir_Kind_Right_Type_Attribute => diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb index 503d43293..7e6785a2b 100644 --- a/src/vhdl/vhdl-sem.adb +++ b/src/vhdl/vhdl-sem.adb @@ -462,6 +462,31 @@ package body Vhdl.Sem is Res := Sem_Generic_Association_Chain (Inter_Parent, Assoc_Parent); end Sem_Generic_Association_Chain; + -- LRM08 6.5.6.3 Port clauses + function Sem_Insert_Anonymous_Signal (Formal : Iir; Actual : Iir) + return Iir + is + Sig : Iir; + Res : Iir; + begin + -- Create the anonymous signal. + Sig := Create_Iir (Iir_Kind_Anonymous_Signal_Declaration); + Location_Copy (Sig, Actual); + Set_Expression (Sig, Actual); + Set_Type (Sig, Get_Type (Formal)); + + -- Declare it. + Add_Implicit_Declaration (Sig); + + -- Return a reference to it. + -- FIXME: The referenced name is not a name. + Res := Create_Iir (Iir_Kind_Reference_Name); + Set_Referenced_Name (Res, Sig); + Set_Named_Entity (Res, Sig); + Set_Type (Res, Get_Type (Sig)); + return Res; + end Sem_Insert_Anonymous_Signal; + -- INTER_PARENT contains ports interfaces; -- ASSOC_PARENT constains ports map aspects. procedure Sem_Port_Association_Chain @@ -577,18 +602,24 @@ package body Vhdl.Sem is & "expression"); end if; + -- Is it possible to have a globally static name that is + -- not readable ? + Check_Read (Actual); + -- LRM93 1.1.1.2 Ports -- The actual, if an expression, must be a globally -- static expression. if Get_Expr_Staticness (Actual) < Globally then - Error_Msg_Sem - (+Actual, - "actual expression must be globally static"); + if Flags.Vhdl_Std >= Vhdl_08 then + -- LRM08 6.5.6.3 Port clauses + Actual := Sem_Insert_Anonymous_Signal (Inter, Actual); + Set_Actual (Assoc, Actual); + else + Error_Msg_Sem + (+Actual, + "actual expression must be globally static"); + end if; end if; - - -- Is it possible to have a globally static name that is - -- not readable ? - Check_Read (Actual); else Error_Msg_Sem (+Assoc, diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 9e98c26a3..0f173d923 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -116,6 +116,9 @@ package body Vhdl.Sem_Decls is if Current_Signals_Region.Decls_Parent = Parent and then Current_Signals_Region.Implicit_Decl /= Null_Iir then + -- There are pending implicit declarations. Can happen only + -- during analysis of declarations, therefore when declarations are + -- not fully analyzed. pragma Assert (not Current_Signals_Region.Decls_Analyzed); -- Add pending implicit declarations before the current one. @@ -128,6 +131,22 @@ package body Vhdl.Sem_Decls is end if; end Insert_Pending_Implicit_Declarations; + procedure Add_Implicit_Declaration (Sig : Iir) is + begin + -- Only for anonymous signals, which appear in instantiations (so + -- once the declarations have been analyzed). + pragma Assert (Get_Kind (Sig) = Iir_Kind_Anonymous_Signal_Declaration); + pragma Assert (Current_Signals_Region.Decls_Analyzed); + + if Current_Signals_Region.Last_Decl = Null_Iir then + Set_Declaration_Chain (Current_Signals_Region.Decls_Parent, Sig); + else + Set_Chain (Current_Signals_Region.Last_Decl, Sig); + end if; + Current_Signals_Region.Last_Decl := Sig; + Set_Parent (Sig, Current_Signals_Region.Decls_Parent); + end Add_Implicit_Declaration; + -- Mark the end of declaration analysis. New implicit declarations will -- simply be appended to the last declaration. procedure End_Of_Declarations_For_Implicit_Declarations diff --git a/src/vhdl/vhdl-sem_decls.ads b/src/vhdl/vhdl-sem_decls.ads index f22cd8791..3ab43adf8 100644 --- a/src/vhdl/vhdl-sem_decls.ads +++ b/src/vhdl/vhdl-sem_decls.ads @@ -75,9 +75,14 @@ package Vhdl.Sem_Decls is procedure Pop_Signals_Declarative_Part (Cell: in Implicit_Signal_Declaration_Type); - -- Declare an implicit signal. + -- Declare an implicit signal. This is called from sem_names when a + -- signal attribute is analyzed. procedure Add_Declaration_For_Implicit_Signal (Sig : Iir); + -- Append declaration SIG (for an anonymous signal) to the current + -- declarative part. + procedure Add_Implicit_Declaration (Sig : Iir); + private type Implicit_Signal_Declaration_Type is record -- Declaration or statement than will contain implicit declarations. @@ -92,10 +97,13 @@ private -- If True, declarations of DECLS_PARENT have already been analyzed. -- So implicit declarations are appended to the parent, and the last - -- declaration is LAST_DECL. + -- declaration is LAST_DECL. This is the usual case when attribute + -- signals are used in statements. -- If False, declarations are being analyzed. Implicit declarations -- are appended to IMPLICIT_DECL/LAST_ATTRIBUTE_SIGNAL and will be - -- inserted before the current declaration. + -- inserted before the current declaration. This can happen if a + -- attribute signal is used in a declaration, the attribute signal + -- must be declared before it is used. Decls_Analyzed : Boolean; -- Last declaration in the region. If an implicit_decl is createed, it diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index 35516f6f0..fa57a0d26 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -3345,6 +3345,8 @@ package body Vhdl.Sem_Names is Prefix : Iir; begin Prefix := Get_Named_Entity (Get_Prefix (Attr)); + + -- Create the proper signal attribute node. Res := Create_Iir (Kind); Location_Copy (Res, Attr); if Kind = Iir_Kind_Delayed_Attribute then @@ -3371,6 +3373,8 @@ package body Vhdl.Sem_Names is null; end case; end if; + + -- Add a declaration for it. Sem_Decls.Add_Declaration_For_Implicit_Signal (Res); return Res; end Sem_Signal_Signal_Attribute; diff --git a/src/vhdl/vhdl-utils.adb b/src/vhdl/vhdl-utils.adb index ea269f2cc..8c550ab98 100644 --- a/src/vhdl/vhdl-utils.adb +++ b/src/vhdl/vhdl-utils.adb @@ -163,7 +163,8 @@ package body Vhdl.Utils is end case; end Get_Operator_Name; - function Get_Longuest_Static_Prefix (Expr: Iir) return Iir is + function Get_Longuest_Static_Prefix (Expr: Iir) return Iir + is Adecl: Iir; begin Adecl := Expr; @@ -177,6 +178,7 @@ package body Vhdl.Utils is return Adecl; when Iir_Kind_Signal_Declaration | Iir_Kind_Guard_Signal_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Interface_Signal_Declaration => return Adecl; when Iir_Kind_Object_Alias_Declaration => @@ -297,6 +299,7 @@ package body Vhdl.Utils is | Iir_Kind_Scalar_Nature_Definition | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration + | Iir_Kind_Anonymous_Signal_Declaration | Iir_Kind_Signal_Attribute_Declaration | Iir_Kind_Unaffected_Waveform | Iir_Kind_Waveform_Element |