diff options
| -rw-r--r-- | python/libghdl/thin/std_names.py | 343 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 206 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/tokens.py | 26 | ||||
| -rw-r--r-- | src/ghdldrv/ghdl_llvm.adb | 2 | ||||
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 7 | ||||
| -rw-r--r-- | src/synth/ghdlsynth_gates.h | 9 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 9 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 13 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 32 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 20 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 9 |
14 files changed, 382 insertions, 307 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index 68f8aad32..e84884895 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -589,174 +589,175 @@ class Name: To_Unsigned = 803 To_Signed = 804 Resize = 805 - Math_Real = 806 - Ceil = 807 - Log2 = 808 - Last_Ieee = 808 - First_Directive = 809 - Define = 809 - Endif = 810 - Ifdef = 811 - Ifndef = 812 - Include = 813 - Timescale = 814 - Undef = 815 - Protect = 816 - Begin_Protected = 817 - End_Protected = 818 - Key_Block = 819 - Data_Block = 820 - Line = 821 - Celldefine = 822 - Endcelldefine = 823 - Default_Nettype = 824 - Resetall = 825 - Last_Directive = 825 - First_Systask = 826 - Bits = 826 - D_Root = 827 - D_Unit = 828 - Last_Systask = 828 - First_SV_Method = 829 - Size = 829 - Insert = 830 - Delete = 831 - Pop_Front = 832 - Pop_Back = 833 - Push_Front = 834 - Push_Back = 835 - Name = 836 - Len = 837 - Substr = 838 - Exists = 839 - Atoi = 840 - Itoa = 841 - Find = 842 - Find_Index = 843 - Find_First = 844 - Find_First_Index = 845 - Find_Last = 846 - Find_Last_Index = 847 - Num = 848 - Randomize = 849 - Pre_Randomize = 850 - Post_Randomize = 851 - Srandom = 852 - Get_Randstate = 853 - Set_Randstate = 854 - Seed = 855 - State = 856 - Last_SV_Method = 856 - First_BSV = 857 - uAction = 857 - uActionValue = 858 - BVI = 859 - uC = 860 - uCF = 861 - uE = 862 - uSB = 863 - uSBR = 864 - Action = 865 - Endaction = 866 - Actionvalue = 867 - Endactionvalue = 868 - Ancestor = 869 - Clocked_By = 870 - Default_Clock = 871 - Default_Reset = 872 - Dependencies = 873 - Deriving = 874 - Determines = 875 - Enable = 876 - Ifc_Inout = 877 - Input_Clock = 878 - Input_Reset = 879 - Instance = 880 - Endinstance = 881 - Let = 882 - Match = 883 - Method = 884 - Endmethod = 885 - Numeric = 886 - Output_Clock = 887 - Output_Reset = 888 - Par = 889 - Endpar = 890 - Path = 891 - Provisos = 892 - Ready = 893 - Reset_By = 894 - Rule = 895 - Endrule = 896 - Rules = 897 - Endrules = 898 - Same_Family = 899 - Schedule = 900 - Seq = 901 - Endseq = 902 - Typeclass = 903 - Endtypeclass = 904 - Valueof = 905 - uValueof = 906 - Last_BSV = 906 - First_Comment = 907 - Psl = 907 - Pragma = 908 - Last_Comment = 908 - First_PSL = 909 - A = 909 - Af = 910 - Ag = 911 - Ax = 912 - Abort = 913 - Assume_Guarantee = 914 - Before = 915 - Clock = 916 - E = 917 - Ef = 918 - Eg = 919 - Ex = 920 - Endpoint = 921 - Eventually = 922 - Fairness = 923 - Fell = 924 - Forall = 925 - G = 926 - Inf = 927 - Inherit = 928 - Never = 929 - Next_A = 930 - Next_E = 931 - Next_Event = 932 - Next_Event_A = 933 - Next_Event_E = 934 - Prev = 935 - Rose = 936 - Strong = 937 - W = 938 - Whilenot = 939 - Within = 940 - X = 941 - Last_PSL = 941 - First_Edif = 942 - Celltype = 952 - View = 953 - Viewtype = 954 - Direction = 955 - Contents = 956 - Net = 957 - Viewref = 958 - Cellref = 959 - Libraryref = 960 - Portinstance = 961 - Joined = 962 - Portref = 963 - Instanceref = 964 - Design = 965 - Designator = 966 - Owner = 967 - Member = 968 - Number = 969 - Rename = 970 - Userdata = 971 - Last_Edif = 971 + Std_Match = 806 + Math_Real = 807 + Ceil = 808 + Log2 = 809 + Last_Ieee = 809 + First_Directive = 810 + Define = 810 + Endif = 811 + Ifdef = 812 + Ifndef = 813 + Include = 814 + Timescale = 815 + Undef = 816 + Protect = 817 + Begin_Protected = 818 + End_Protected = 819 + Key_Block = 820 + Data_Block = 821 + Line = 822 + Celldefine = 823 + Endcelldefine = 824 + Default_Nettype = 825 + Resetall = 826 + Last_Directive = 826 + First_Systask = 827 + Bits = 827 + D_Root = 828 + D_Unit = 829 + Last_Systask = 829 + First_SV_Method = 830 + Size = 830 + Insert = 831 + Delete = 832 + Pop_Front = 833 + Pop_Back = 834 + Push_Front = 835 + Push_Back = 836 + Name = 837 + Len = 838 + Substr = 839 + Exists = 840 + Atoi = 841 + Itoa = 842 + Find = 843 + Find_Index = 844 + Find_First = 845 + Find_First_Index = 846 + Find_Last = 847 + Find_Last_Index = 848 + Num = 849 + Randomize = 850 + Pre_Randomize = 851 + Post_Randomize = 852 + Srandom = 853 + Get_Randstate = 854 + Set_Randstate = 855 + Seed = 856 + State = 857 + Last_SV_Method = 857 + First_BSV = 858 + uAction = 858 + uActionValue = 859 + BVI = 860 + uC = 861 + uCF = 862 + uE = 863 + uSB = 864 + uSBR = 865 + Action = 866 + Endaction = 867 + Actionvalue = 868 + Endactionvalue = 869 + Ancestor = 870 + Clocked_By = 871 + Default_Clock = 872 + Default_Reset = 873 + Dependencies = 874 + Deriving = 875 + Determines = 876 + Enable = 877 + Ifc_Inout = 878 + Input_Clock = 879 + Input_Reset = 880 + Instance = 881 + Endinstance = 882 + Let = 883 + Match = 884 + Method = 885 + Endmethod = 886 + Numeric = 887 + Output_Clock = 888 + Output_Reset = 889 + Par = 890 + Endpar = 891 + Path = 892 + Provisos = 893 + Ready = 894 + Reset_By = 895 + Rule = 896 + Endrule = 897 + Rules = 898 + Endrules = 899 + Same_Family = 900 + Schedule = 901 + Seq = 902 + Endseq = 903 + Typeclass = 904 + Endtypeclass = 905 + Valueof = 906 + uValueof = 907 + Last_BSV = 907 + First_Comment = 908 + Psl = 908 + Pragma = 909 + Last_Comment = 909 + First_PSL = 910 + A = 910 + Af = 911 + Ag = 912 + Ax = 913 + Abort = 914 + Assume_Guarantee = 915 + Before = 916 + Clock = 917 + E = 918 + Ef = 919 + Eg = 920 + Ex = 921 + Endpoint = 922 + Eventually = 923 + Fairness = 924 + Fell = 925 + Forall = 926 + G = 927 + Inf = 928 + Inherit = 929 + Never = 930 + Next_A = 931 + Next_E = 932 + Next_Event = 933 + Next_Event_A = 934 + Next_Event_E = 935 + Prev = 936 + Rose = 937 + Strong = 938 + W = 939 + Whilenot = 940 + Within = 941 + X = 942 + Last_PSL = 942 + First_Edif = 943 + Celltype = 953 + View = 954 + Viewtype = 955 + Direction = 956 + Contents = 957 + Net = 958 + Viewref = 959 + Cellref = 960 + Libraryref = 961 + Portinstance = 962 + Joined = 963 + Portref = 964 + Instanceref = 965 + Design = 966 + Designator = 967 + Owner = 968 + Member = 969 + Number = 970 + Rename = 971 + Userdata = 972 + Last_Edif = 972 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 380974b7b..8b99eefc4 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1058,105 +1058,113 @@ class Iir_Predefined: Ieee_1164_Vector_Xor = 183 Ieee_1164_Vector_Xnor = 184 Ieee_1164_Vector_Not = 185 - Ieee_Numeric_Std_Toint_Uns_Nat = 186 - Ieee_Numeric_Std_Toint_Sgn_Int = 187 - Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 188 - Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 189 - Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 190 - Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 191 - Ieee_Numeric_Std_Resize_Uns_Nat = 192 - Ieee_Numeric_Std_Resize_Sgn_Nat = 193 - Ieee_Numeric_Std_Resize_Uns_Uns = 194 - Ieee_Numeric_Std_Resize_Sgn_Sgn = 195 - Ieee_Numeric_Std_Add_Uns_Uns = 196 - Ieee_Numeric_Std_Add_Uns_Nat = 197 - Ieee_Numeric_Std_Add_Nat_Uns = 198 - Ieee_Numeric_Std_Add_Sgn_Sgn = 199 - Ieee_Numeric_Std_Add_Sgn_Int = 200 - Ieee_Numeric_Std_Add_Int_Sgn = 201 - Ieee_Numeric_Std_Sub_Uns_Uns = 202 - Ieee_Numeric_Std_Sub_Uns_Nat = 203 - Ieee_Numeric_Std_Sub_Nat_Uns = 204 - Ieee_Numeric_Std_Sub_Sgn_Sgn = 205 - Ieee_Numeric_Std_Sub_Sgn_Int = 206 - Ieee_Numeric_Std_Sub_Int_Sgn = 207 - Ieee_Numeric_Std_Gt_Uns_Uns = 208 - Ieee_Numeric_Std_Gt_Uns_Nat = 209 - Ieee_Numeric_Std_Gt_Nat_Uns = 210 - Ieee_Numeric_Std_Gt_Sgn_Sgn = 211 - Ieee_Numeric_Std_Gt_Sgn_Int = 212 - Ieee_Numeric_Std_Gt_Int_Sgn = 213 - Ieee_Numeric_Std_Lt_Uns_Uns = 214 - Ieee_Numeric_Std_Lt_Uns_Nat = 215 - Ieee_Numeric_Std_Lt_Nat_Uns = 216 - Ieee_Numeric_Std_Lt_Sgn_Sgn = 217 - Ieee_Numeric_Std_Lt_Sgn_Int = 218 - Ieee_Numeric_Std_Lt_Int_Sgn = 219 - Ieee_Numeric_Std_Le_Uns_Uns = 220 - Ieee_Numeric_Std_Le_Uns_Nat = 221 - Ieee_Numeric_Std_Le_Nat_Uns = 222 - Ieee_Numeric_Std_Le_Sgn_Sgn = 223 - Ieee_Numeric_Std_Le_Sgn_Int = 224 - Ieee_Numeric_Std_Le_Int_Sgn = 225 - Ieee_Numeric_Std_Ge_Uns_Uns = 226 - Ieee_Numeric_Std_Ge_Uns_Nat = 227 - Ieee_Numeric_Std_Ge_Nat_Uns = 228 - Ieee_Numeric_Std_Ge_Sgn_Sgn = 229 - Ieee_Numeric_Std_Ge_Sgn_Int = 230 - Ieee_Numeric_Std_Ge_Int_Sgn = 231 - Ieee_Numeric_Std_Eq_Uns_Uns = 232 - Ieee_Numeric_Std_Eq_Uns_Nat = 233 - Ieee_Numeric_Std_Eq_Nat_Uns = 234 - Ieee_Numeric_Std_Eq_Sgn_Sgn = 235 - Ieee_Numeric_Std_Eq_Sgn_Int = 236 - Ieee_Numeric_Std_Eq_Int_Sgn = 237 - Ieee_Numeric_Std_Ne_Uns_Uns = 238 - Ieee_Numeric_Std_Ne_Uns_Nat = 239 - Ieee_Numeric_Std_Ne_Nat_Uns = 240 - Ieee_Numeric_Std_Ne_Sgn_Sgn = 241 - Ieee_Numeric_Std_Ne_Sgn_Int = 242 - Ieee_Numeric_Std_Ne_Int_Sgn = 243 - Ieee_Numeric_Std_Not_Uns = 244 - Ieee_Numeric_Std_Not_Sgn = 245 - Ieee_Numeric_Std_And_Uns_Uns = 246 - Ieee_Numeric_Std_And_Sgn_Sgn = 247 - Ieee_Numeric_Std_Or_Uns_Uns = 248 - Ieee_Numeric_Std_Or_Sgn_Sgn = 249 - Ieee_Numeric_Std_Nand_Uns_Uns = 250 - Ieee_Numeric_Std_Nand_Sgn_Sgn = 251 - Ieee_Numeric_Std_Nor_Uns_Uns = 252 - Ieee_Numeric_Std_Nor_Sgn_Sgn = 253 - Ieee_Numeric_Std_Xor_Uns_Uns = 254 - Ieee_Numeric_Std_Xor_Sgn_Sgn = 255 - Ieee_Numeric_Std_Xnor_Uns_Uns = 256 - Ieee_Numeric_Std_Xnor_Sgn_Sgn = 257 - Ieee_Numeric_Std_Neg_Uns = 258 - Ieee_Numeric_Std_Neg_Sgn = 259 - Ieee_Math_Real_Ceil = 260 - Ieee_Math_Real_Log2 = 261 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 262 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 263 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 264 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 265 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 266 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 267 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 268 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 269 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 270 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 271 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 272 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 273 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 274 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 275 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 276 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 277 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 278 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 279 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 280 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 281 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 282 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 283 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 284 + Ieee_1164_Vector_And_Reduce = 186 + Ieee_1164_Vector_Or_Reduce = 187 + Ieee_1164_Condition_Operator = 188 + Ieee_Numeric_Std_Toint_Uns_Nat = 189 + Ieee_Numeric_Std_Toint_Sgn_Int = 190 + Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 191 + Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 192 + Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 193 + Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 194 + Ieee_Numeric_Std_Resize_Uns_Nat = 195 + Ieee_Numeric_Std_Resize_Sgn_Nat = 196 + Ieee_Numeric_Std_Resize_Uns_Uns = 197 + Ieee_Numeric_Std_Resize_Sgn_Sgn = 198 + Ieee_Numeric_Std_Add_Uns_Uns = 199 + Ieee_Numeric_Std_Add_Uns_Nat = 200 + Ieee_Numeric_Std_Add_Nat_Uns = 201 + Ieee_Numeric_Std_Add_Sgn_Sgn = 202 + Ieee_Numeric_Std_Add_Sgn_Int = 203 + Ieee_Numeric_Std_Add_Int_Sgn = 204 + Ieee_Numeric_Std_Sub_Uns_Uns = 205 + Ieee_Numeric_Std_Sub_Uns_Nat = 206 + Ieee_Numeric_Std_Sub_Nat_Uns = 207 + Ieee_Numeric_Std_Sub_Sgn_Sgn = 208 + Ieee_Numeric_Std_Sub_Sgn_Int = 209 + Ieee_Numeric_Std_Sub_Int_Sgn = 210 + Ieee_Numeric_Std_Gt_Uns_Uns = 211 + Ieee_Numeric_Std_Gt_Uns_Nat = 212 + Ieee_Numeric_Std_Gt_Nat_Uns = 213 + Ieee_Numeric_Std_Gt_Sgn_Sgn = 214 + Ieee_Numeric_Std_Gt_Sgn_Int = 215 + Ieee_Numeric_Std_Gt_Int_Sgn = 216 + Ieee_Numeric_Std_Lt_Uns_Uns = 217 + Ieee_Numeric_Std_Lt_Uns_Nat = 218 + Ieee_Numeric_Std_Lt_Nat_Uns = 219 + Ieee_Numeric_Std_Lt_Sgn_Sgn = 220 + Ieee_Numeric_Std_Lt_Sgn_Int = 221 + Ieee_Numeric_Std_Lt_Int_Sgn = 222 + Ieee_Numeric_Std_Le_Uns_Uns = 223 + Ieee_Numeric_Std_Le_Uns_Nat = 224 + Ieee_Numeric_Std_Le_Nat_Uns = 225 + Ieee_Numeric_Std_Le_Sgn_Sgn = 226 + Ieee_Numeric_Std_Le_Sgn_Int = 227 + Ieee_Numeric_Std_Le_Int_Sgn = 228 + Ieee_Numeric_Std_Ge_Uns_Uns = 229 + Ieee_Numeric_Std_Ge_Uns_Nat = 230 + Ieee_Numeric_Std_Ge_Nat_Uns = 231 + Ieee_Numeric_Std_Ge_Sgn_Sgn = 232 + Ieee_Numeric_Std_Ge_Sgn_Int = 233 + Ieee_Numeric_Std_Ge_Int_Sgn = 234 + Ieee_Numeric_Std_Eq_Uns_Uns = 235 + Ieee_Numeric_Std_Eq_Uns_Nat = 236 + Ieee_Numeric_Std_Eq_Nat_Uns = 237 + Ieee_Numeric_Std_Eq_Sgn_Sgn = 238 + Ieee_Numeric_Std_Eq_Sgn_Int = 239 + Ieee_Numeric_Std_Eq_Int_Sgn = 240 + Ieee_Numeric_Std_Ne_Uns_Uns = 241 + Ieee_Numeric_Std_Ne_Uns_Nat = 242 + Ieee_Numeric_Std_Ne_Nat_Uns = 243 + Ieee_Numeric_Std_Ne_Sgn_Sgn = 244 + Ieee_Numeric_Std_Ne_Sgn_Int = 245 + Ieee_Numeric_Std_Ne_Int_Sgn = 246 + Ieee_Numeric_Std_Not_Uns = 247 + Ieee_Numeric_Std_Not_Sgn = 248 + Ieee_Numeric_Std_And_Uns_Uns = 249 + Ieee_Numeric_Std_And_Sgn_Sgn = 250 + Ieee_Numeric_Std_Or_Uns_Uns = 251 + Ieee_Numeric_Std_Or_Sgn_Sgn = 252 + Ieee_Numeric_Std_Nand_Uns_Uns = 253 + Ieee_Numeric_Std_Nand_Sgn_Sgn = 254 + Ieee_Numeric_Std_Nor_Uns_Uns = 255 + Ieee_Numeric_Std_Nor_Sgn_Sgn = 256 + Ieee_Numeric_Std_Xor_Uns_Uns = 257 + Ieee_Numeric_Std_Xor_Sgn_Sgn = 258 + Ieee_Numeric_Std_Xnor_Uns_Uns = 259 + Ieee_Numeric_Std_Xnor_Sgn_Sgn = 260 + Ieee_Numeric_Std_Neg_Uns = 261 + Ieee_Numeric_Std_Neg_Sgn = 262 + Ieee_Numeric_Std_Match_Log = 263 + Ieee_Numeric_Std_Match_Uns = 264 + Ieee_Numeric_Std_Match_Sgn = 265 + Ieee_Numeric_Std_Match_Slv = 266 + Ieee_Numeric_Std_Match_Suv = 267 + Ieee_Math_Real_Ceil = 268 + Ieee_Math_Real_Log2 = 269 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 270 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 271 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 272 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 273 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 274 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 275 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 276 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 277 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 278 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 279 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 280 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 281 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 282 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 283 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 284 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 285 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 286 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 287 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 288 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 289 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 290 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 291 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 292 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/python/libghdl/thin/vhdl/tokens.py b/python/libghdl/thin/vhdl/tokens.py index 67bf038e7..db2741d34 100644 --- a/python/libghdl/thin/vhdl/tokens.py +++ b/python/libghdl/thin/vhdl/tokens.py @@ -196,14 +196,20 @@ class Tok: Before_Em = 192 Before_Un = 193 Before_Em_Un = 194 - Until_Em = 195 - Until_Un = 196 - Until_Em_Un = 197 - Always = 198 - Never = 199 - Eventually = 200 - Next_A = 201 - Next_E = 202 + Always = 195 + Never = 196 + Eventually_Em = 197 + Next_Em = 198 + Next_A = 199 + Next_A_Em = 200 + Next_E = 201 + Next_E_Em = 202 Next_Event = 203 - Next_Event_A = 204 - Next_Event_E = 205 + Next_Event_Em = 204 + Next_Event_A = 205 + Next_Event_A_Em = 206 + Next_Event_E = 207 + Next_Event_E_Em = 208 + Until_Em = 209 + Until_Un = 210 + Until_Em_Un = 211 diff --git a/src/ghdldrv/ghdl_llvm.adb b/src/ghdldrv/ghdl_llvm.adb index c170c4b56..f18741bd6 100644 --- a/src/ghdldrv/ghdl_llvm.adb +++ b/src/ghdldrv/ghdl_llvm.adb @@ -21,6 +21,7 @@ with Ghdlprint; with Ghdldrv; with Ghdlvpi; with Ghdlxml; +with Ghdlsynth_Maybe; procedure Ghdl_Llvm is begin @@ -29,6 +30,7 @@ begin Ghdlmain.Version_String := new String'("llvm code generator"); Ghdldrv.Backend := Ghdldrv.Backend_Llvm; Ghdldrv.Register_Commands; + Ghdlsynth_Maybe.Register_Commands; Ghdllocal.Register_Commands; Ghdlprint.Register_Commands; Ghdlvpi.Register_Commands; diff --git a/src/std_names.adb b/src/std_names.adb index bdc11e695..34aae433c 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -641,6 +641,7 @@ package body Std_Names is Def ("to_unsigned", Name_To_Unsigned); Def ("to_signed", Name_To_Signed); Def ("resize", Name_Resize); + Def ("std_match", Name_Std_Match); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index a00d89585..e20db31a9 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -722,9 +722,10 @@ package Std_Names is Name_To_Unsigned : constant Name_Id := Name_First_Ieee + 020; Name_To_Signed : constant Name_Id := Name_First_Ieee + 021; Name_Resize : constant Name_Id := Name_First_Ieee + 022; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 023; - Name_Ceil : constant Name_Id := Name_First_Ieee + 024; - Name_Log2 : constant Name_Id := Name_First_Ieee + 025; + Name_Std_Match : constant Name_Id := Name_First_Ieee + 023; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 024; + Name_Ceil : constant Name_Id := Name_First_Ieee + 025; + Name_Log2 : constant Name_Id := Name_First_Ieee + 026; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h index a8dfe2a7f..bef7a7d97 100644 --- a/src/synth/ghdlsynth_gates.h +++ b/src/synth/ghdlsynth_gates.h @@ -1,4 +1,5 @@ -/* This file is automatically generated by build_header.sh - DO NOT MODIFY */ +/* DO NOT MODIFY + This file is automatically generated by Makefile. */ enum Module_Id { Id_None = 0, Id_Free = 1, @@ -57,12 +58,8 @@ enum Module_Id { Id_Assume = 57, Id_Const_UB32 = 64, Id_Const_UL32 = 70, - Id_Const_SB32 = 65, Id_Const_UB64 = 66, - Id_Const_SB64 = 67, - Id_Const_UB128 = 68, - Id_Const_SB128 = 69, - Id_Const_SL32 = 71, + Id_Const_UL64 = 67, Id_Const_Z = 72, Id_Const_0 = 73, Id_Const_Bit = 74, diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 649503796..da72811e0 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -144,16 +144,11 @@ package Netlists.Gates is -- Constants are gates with only one constant output. There are multiple -- kind of constant gates: for small width, the value is stored as a - -- parameter, possibly signed or unsigned extended. For large width - -- (> 128), the value is stored in a table. + -- parameter, possibly signed or unsigned extended. Id_Const_UB32 : constant Module_Id := 64; Id_Const_UL32 : constant Module_Id := 70; - Id_Const_SB32 : constant Module_Id := 65; Id_Const_UB64 : constant Module_Id := 66; - Id_Const_SB64 : constant Module_Id := 67; - Id_Const_UB128 : constant Module_Id := 68; - Id_Const_SB128 : constant Module_Id := 69; - Id_Const_SL32 : constant Module_Id := 71; + Id_Const_UL64 : constant Module_Id := 67; Id_Const_Z : constant Module_Id := 72; Id_Const_0 : constant Module_Id := 73; diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 6fdd413a5..4d443d999 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -43,6 +43,10 @@ with Netlists.Builders; use Netlists.Builders; with Netlists.Locations; use Netlists.Locations; package body Synth.Expr is + -- As log2(3m) is directly referenced, the program must be linked with -lm + -- (math library) on unix systems. + pragma Linker_Options ("-lm"); + function Synth_Name (Syn_Inst : Synth_Instance_Acc; Name : Node) return Value_Acc; @@ -373,7 +377,9 @@ package body Synth.Expr is end if; end loop; when Iir_Kind_Choice_By_Name => - Pos := Natural (Get_Element_Position (Get_Name (Assoc))); + Pos := Natural (Get_Element_Position + (Get_Named_Entity + (Get_Choice_Name (Assoc)))); Set_Elem (Pos); when others => Error_Msg_Synth @@ -586,7 +592,8 @@ package body Synth.Expr is case Get_Kind (Bound) is when Iir_Kind_Range_Expression => return Synth_Discrete_Range_Expression (Syn_Inst, Bound); - when Iir_Kind_Integer_Subtype_Definition => + when Iir_Kind_Integer_Subtype_Definition + | Iir_Kind_Enumeration_Subtype_Definition => if Get_Type_Declarator (Bound) /= Null_Node then -- This is a named subtype, so it has been evaluated. return Get_Value_Type (Syn_Inst, Bound).Drange; @@ -1394,6 +1401,8 @@ package body Synth.Expr is return Synth_Vec_Reduce_Monadic(Id_Red_And); when Iir_Predefined_Ieee_1164_Vector_Or_Reduce => return Synth_Vec_Reduce_Monadic(Id_Red_Or); + when Iir_Predefined_Ieee_1164_Condition_Operator => + return Operand; when others => Error_Msg_Synth (+Loc, diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 1a3805c77..c36400e91 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1019,8 +1019,6 @@ package body Synth.Stmts is while Is_Valid (Assoc) loop Inter := Get_Association_Interface (Assoc, Assoc_Inter); - Synth_Declaration_Type (Subprg_Inst, Inter); - case Iir_Parameter_Modes (Get_Mode (Inter)) is when Iir_In_Mode => case Get_Kind (Assoc) is @@ -1230,6 +1228,8 @@ package body Synth.Stmts is exit; when Iir_Kind_Procedure_Call_Statement => Synth_Procedure_Call (Syn_Inst, Stmt); + when Iir_Kind_Report_Statement => + null; when others => Error_Kind ("synth_sequential_statements", Stmt); end case; diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index d81e70adf..0b15f37b0 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -487,7 +487,10 @@ package body Vhdl.Annotations is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_File_Declaration => - Annotate_Anonymous_Type_Definition (Block_Info, Get_Type (El)); + if Get_Subtype_Indication (El) /= Null_Iir then + Annotate_Anonymous_Type_Definition + (Block_Info, Get_Type (El)); + end if; when others => Error_Kind ("annotate_interface_list_subtype", El); end case; @@ -877,7 +880,8 @@ package body Vhdl.Annotations is when Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement - | Iir_Kind_Variable_Assignment_Statement => + | Iir_Kind_Variable_Assignment_Statement + | Iir_Kind_Conditional_Variable_Assignment_Statement => null; when Iir_Kind_Procedure_Call_Statement => null; diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 4a9ba8508..a1ac7927e 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -429,6 +429,36 @@ package body Vhdl.Ieee.Numeric is raise Error; end if; end Handle_Resize; + + procedure Handle_Std_Match + is + Predefined : Iir_Predefined_Functions; + begin + if Arg1_Kind /= Arg2_Kind or else Arg1_Sign /= Arg2_Sign then + raise Error; + end if; + + if Arg1_Kind = Arg_Scal and Arg1_Sign = Type_Log then + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Log; + elsif Arg1_Kind = Arg_Vect then + case Arg1_Sign is + when Type_Unsigned => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Uns; + when Type_Signed => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Sgn; + when Type_Suv => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Suv; + when Type_Slv => + Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Slv; + when Type_Log => + raise Error; + end case; + else + raise Error; + end if; + + Set_Implicit_Definition (Decl, Predefined); + end Handle_Std_Match; begin Decl := Get_Declaration_Chain (Pkg_Decl); @@ -537,6 +567,8 @@ package body Vhdl.Ieee.Numeric is Handle_To_Signed; when Name_Resize => Handle_Resize; + when Name_Std_Match => + Handle_Std_Match; when others => null; end case; diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 14468e1c4..7ea7da787 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -250,11 +250,21 @@ package body Vhdl.Ieee.Std_Logic_1164 is end case; Set_Implicit_Definition (Decl, Predefined); end; - elsif Is_Scalar_Function (Decl) - and then Get_Identifier (Decl) = Name_Not - then - Set_Implicit_Definition - (Decl, Iir_Predefined_Ieee_1164_Scalar_Not); + elsif Is_Scalar_Function (Decl) then + declare + Predefined : Iir_Predefined_Functions; + begin + case Get_Identifier (Decl) is + when Name_Not => + Predefined := Iir_Predefined_Ieee_1164_Scalar_Not; + when Name_Op_Condition => + Predefined := + Iir_Predefined_Ieee_1164_Condition_Operator; + when others => + Predefined := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Predefined); + end; elsif Is_Vector_Vector_Function (Decl) then declare Predefined : Iir_Predefined_Functions; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 41ef5fd9e..3a2bcb20b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4905,6 +4905,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Vector_And_Reduce, Iir_Predefined_Ieee_1164_Vector_Or_Reduce, + Iir_Predefined_Ieee_1164_Condition_Operator, + -- Numeric_Std. -- Abbreviations: -- Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer. @@ -5003,6 +5005,13 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Neg_Uns, Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn, + -- Std_Match functions. + Iir_Predefined_Ieee_Numeric_Std_Match_Log, + Iir_Predefined_Ieee_Numeric_Std_Match_Uns, + Iir_Predefined_Ieee_Numeric_Std_Match_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Match_Slv, + Iir_Predefined_Ieee_Numeric_Std_Match_Suv, + -- Math_Real Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Log2, |