diff options
27 files changed, 481 insertions, 74 deletions
diff --git a/scripts/vendors/compile-altera.ps1 b/scripts/vendors/compile-altera.ps1 index 4efa91b78..0c1f948cf 100644 --- a/scripts/vendors/compile-altera.ps1 +++ b/scripts/vendors/compile-altera.ps1 @@ -118,7 +118,7 @@ if ($All) function Get-AlteraQuartusDirectory { if (Test-Path env:QUARTUS_ROOTDIR) - { return $QUARTUS_ROOTDIR + "\" + (Get-VendorToolSourceDirectory) } + { return $env:QUARTUS_ROOTDIR + "\" + (Get-VendorToolSourceDirectory) } else { $EnvSourceDir = "" foreach ($Drive in Get-PSDrive -PSProvider 'FileSystem') @@ -465,7 +465,7 @@ if ((-not $StopCompiling) -and $Cyclone) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -482,7 +482,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -497,7 +497,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -514,7 +514,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -529,7 +529,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -544,7 +544,7 @@ if ((-not $StopCompiling) -and $Nanometer) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -563,7 +563,7 @@ if ((-not $StopCompiling) -and $Nanometer) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } diff --git a/scripts/vendors/compile-intel.ps1 b/scripts/vendors/compile-intel.ps1 index e2bd259d0..0e3ba781c 100644 --- a/scripts/vendors/compile-intel.ps1 +++ b/scripts/vendors/compile-intel.ps1 @@ -118,7 +118,7 @@ if ($All) function Get-AlteraQuartusDirectory { if (Test-Path env:QUARTUS_ROOTDIR) - { return $QUARTUS_ROOTDIR + "\" + (Get-VendorToolSourceDirectory) } + { return $env:QUARTUS_ROOTDIR + "\" + (Get-VendorToolSourceDirectory) } else { $EnvSourceDir = "" foreach ($Drive in Get-PSDrive -PSProvider 'FileSystem') @@ -433,7 +433,7 @@ if ((-not $StopCompiling) -and $Cyclone) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -448,7 +448,7 @@ if ((-not $StopCompiling) -and $Cyclone) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -465,7 +465,7 @@ if ((-not $StopCompiling) -and $Cyclone) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -482,7 +482,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -497,7 +497,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -514,7 +514,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -529,7 +529,7 @@ if ((-not $StopCompiling) -and $Stratix) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -544,7 +544,7 @@ if ((-not $StopCompiling) -and $Nanometer) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } @@ -563,7 +563,7 @@ if ((-not $StopCompiling) -and $Nanometer) $SourceFiles = $Files | % { "$SourceDirectory\$_" } if (Test-Path $SourceFiles[0]) - { $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + { $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } } diff --git a/scripts/vendors/compile-lattice.ps1 b/scripts/vendors/compile-lattice.ps1 index ca002be4e..7e36c322d 100644 --- a/scripts/vendors/compile-lattice.ps1 +++ b/scripts/vendors/compile-lattice.ps1 @@ -146,7 +146,7 @@ if ($All) function Get-LatticeDiamondDirectory { if (Test-Path env:FOUNDRY) - { return $FOUNDRY + "\..\" + (Get-VendorToolSourceDirectory) } + { return $env:FOUNDRY + "\..\" + (Get-VendorToolSourceDirectory) } else { $EnvSourceDir = "" foreach ($Drive in Get-PSDrive -PSProvider 'FileSystem') @@ -370,7 +370,7 @@ if ((-not $StopCompiling) -and $xp) { $Library = "xp" $SourceFiles = $FileLists[$Library] | % { "$SourceDirectory\$Library\src\$_" } - $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } @@ -380,7 +380,7 @@ if ((-not $StopCompiling) -and $xp2) { $Library = "xp2" $SourceFiles = $FileLists[$Library] | % { "$SourceDirectory\$Library\src\$_" } - $ErrorCount += Start-PackageCompilation $GHDLBinary $GHDLOptions $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug + $ErrorCount += Start-PackageCompilation $GHDLBinary $Analyze_Parameters $DestinationDirectory $Library $VHDLVersion $SourceFiles $SuppressWarnings $HaltOnError -Verbose:$EnableVerbose -Debug:$EnableDebug $StopCompiling = $HaltOnError -and ($ErrorCount -ne 0) } diff --git a/scripts/vendors/compile-xilinx-ise.ps1 b/scripts/vendors/compile-xilinx-ise.ps1 index 947d70fd9..39b363117 100644 --- a/scripts/vendors/compile-xilinx-ise.ps1 +++ b/scripts/vendors/compile-xilinx-ise.ps1 @@ -108,7 +108,7 @@ if ($All) function Get-XilinxISEDirectory { if (Test-Path env:XILINX) - { return $XILINX + "\" + (Get-VendorToolSourceDirectory) } + { return $env:XILINX + "\" + (Get-VendorToolSourceDirectory) } else { $EnvSourceDir = "" foreach ($Drive in Get-PSDrive -PSProvider 'FileSystem') diff --git a/scripts/vendors/compile-xilinx-vivado.ps1 b/scripts/vendors/compile-xilinx-vivado.ps1 index 790dd09a5..a411ababa 100644 --- a/scripts/vendors/compile-xilinx-vivado.ps1 +++ b/scripts/vendors/compile-xilinx-vivado.ps1 @@ -99,7 +99,7 @@ if ($All) function Get-XilinxVivadoDirectory { if (Test-Path env:XILINX_VIVADO) - { return $XILINX_VIVADO + "\" + (Get-VendorToolSourceDirectory) } + { return $env:XILINX_VIVADO + "\" + (Get-VendorToolSourceDirectory) } else { $EnvSourceDir = "" foreach ($Drive in Get-PSDrive -PSProvider 'FileSystem') diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb index 7d726d154..54bd3469b 100644 --- a/src/synth/elab-vhdl_types.adb +++ b/src/synth/elab-vhdl_types.adb @@ -198,6 +198,8 @@ package body Elab.Vhdl_Types is function Synth_Record_Type_Definition (Syn_Inst : Synth_Instance_Acc; Def : Node) return Type_Acc is + Is_Subtype : constant Boolean := + Get_Kind (Def) = Iir_Kind_Record_Subtype_Definition; El_List : constant Node_Flist := Get_Elements_Declaration_List (Def); Rec_Els : Rec_El_Array_Acc; El : Node; @@ -210,7 +212,13 @@ package body Elab.Vhdl_Types is for I in Flist_First .. Flist_Last (El_List) loop El := Get_Nth_Element (El_List, I); El_Type := Get_Type (El); - El_Typ := Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); + if Is_Subtype then + Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); + El_Typ := Get_Subtype_Object (Syn_Inst, El_Type); + else + El_Typ := Synth_Subtype_Indication_If_Anonymous + (Syn_Inst, El_Type); + end if; Rec_Els.E (Iir_Index32 (I + 1)).Typ := El_Typ; end loop; diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index 90e72f223..017edc700 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -246,9 +246,9 @@ package body Elab.Vhdl_Values is Res.Val.Mem (I - 1) := Src.Val.Mem (I - 1); end loop; when Value_Net => - Res := (Src.Typ, Create_Value_Net (Src.Val.S)); + Res := (Src.Typ, Create_Value_Net (Src.Val.N)); when Value_Wire => - Res := (Src.Typ, Create_Value_Wire (Src.Val.S)); + Res := (Src.Typ, Create_Value_Wire (Src.Val.N)); when Value_File => Res := Create_Value_File (Src.Typ, Src.Val.File); when Value_Signal => diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index ee691d8f5..c7eb117b6 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -893,6 +893,12 @@ package body Synth.Vhdl_Expr is end case; end Synth_Name; + procedure Bound_Error (Syn_Inst : Synth_Instance_Acc; Loc : Node) is + begin + Error_Msg_Synth (+Loc, "index not within bounds"); + Elab.Debugger.Debug_Error (Syn_Inst, Loc); + end Bound_Error; + -- Convert index IDX in PFX to an offset. -- SYN_INST and LOC are used in case of error. function Index_To_Offset @@ -902,8 +908,7 @@ package body Synth.Vhdl_Expr is Res : Value_Offsets; begin if not In_Bounds (Bnd, Int32 (Idx)) then - Error_Msg_Synth (+Loc, "index not within bounds"); - Elab.Debugger.Debug_Error (Syn_Inst, Loc); + Bound_Error (Syn_Inst, Loc); return (0, 0); end if; @@ -1000,13 +1005,15 @@ package body Synth.Vhdl_Expr is Name : Node; Pfx_Type : Type_Acc; Voff : out Net; - Off : out Value_Offsets) + Off : out Value_Offsets; + Error : out Boolean) is Ctxt : constant Context_Acc := Get_Build (Syn_Inst); Indexes : constant Iir_Flist := Get_Index_List (Name); El_Typ : constant Type_Acc := Get_Array_Element (Pfx_Type); Idx_Expr : Node; Idx_Val : Valtyp; + Idx : Int64; Bnd : Bound_Type; Stride : Uns32; Ivoff : Net; @@ -1014,6 +1021,7 @@ package body Synth.Vhdl_Expr is begin Voff := No_Net; Off := (0, 0); + Error := False; Stride := 1; for I in reverse Flist_First .. Flist_Last (Indexes) loop @@ -1022,9 +1030,8 @@ package body Synth.Vhdl_Expr is -- Use the base type as the subtype of the index is not synth-ed. Idx_Val := Synth_Expression_With_Basetype (Syn_Inst, Idx_Expr); if Idx_Val = No_Valtyp then - -- Propagate errorc - Voff := No_Net; - Off := (0, 0); + -- Propagate error. + Error := True; return; end if; @@ -1033,11 +1040,17 @@ package body Synth.Vhdl_Expr is Bnd := Get_Array_Bound (Pfx_Type, Dim_Type (I + 1)); if Is_Static_Val (Idx_Val.Val) then - Idx_Off := Index_To_Offset (Syn_Inst, Bnd, - Get_Static_Discrete (Idx_Val), Name); - Off.Net_Off := Off.Net_Off + Idx_Off.Net_Off * Stride * El_Typ.W; - Off.Mem_Off := Off.Mem_Off - + Idx_Off.Mem_Off * Size_Type (Stride) * El_Typ.Sz; + Idx := Get_Static_Discrete (Idx_Val); + if not In_Bounds (Bnd, Int32 (Idx)) then + Bound_Error (Syn_Inst, Name); + Error := True; + else + Idx_Off := Index_To_Offset (Syn_Inst, Bnd, Idx, Name); + Off.Net_Off := Off.Net_Off + + Idx_Off.Net_Off * Stride * El_Typ.W; + Off.Mem_Off := Off.Mem_Off + + Idx_Off.Mem_Off * Size_Type (Stride) * El_Typ.Sz; + end if; else Ivoff := Dyn_Index_To_Offset (Ctxt, Bnd, Idx_Val, Name); Ivoff := Build_Memidx @@ -2202,6 +2215,10 @@ package body Synth.Vhdl_Expr is Dyn : Dyn_Name; begin Synth_Assignment_Prefix (Syn_Inst, Expr, Base, Typ, Off, Dyn); + if Base = No_Valtyp then + -- Propagate error. + return No_Valtyp; + end if; if Dyn.Voff = No_Net and then Is_Static (Base.Val) then Res := Create_Value_Memory (Typ); Copy_Memory diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads index 7081aef95..33b908de3 100644 --- a/src/synth/synth-vhdl_expr.ads +++ b/src/synth/synth-vhdl_expr.ads @@ -119,7 +119,8 @@ package Synth.Vhdl_Expr is Name : Node; Pfx_Type : Type_Acc; Voff : out Net; - Off : out Value_Offsets); + Off : out Value_Offsets; + Error : out Boolean); -- Conversion to logic vector. type Digit_Index is new Natural; diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index b02d2df69..cd6f55e2a 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -638,11 +638,12 @@ package body Synth.Vhdl_Insts is declare Voff : Net; Arr_Off : Value_Offsets; + Err : Boolean; begin Synth_Individual_Prefix (Syn_Inst, Inter_Inst, Get_Prefix (Formal), Off, Typ); - Synth_Indexed_Name (Syn_Inst, Formal, Typ, Voff, Arr_Off); - if Voff /= No_Net then + Synth_Indexed_Name (Syn_Inst, Formal, Typ, Voff, Arr_Off, Err); + if Voff /= No_Net or Err then raise Internal_Error; end if; Off := Off + Arr_Off.Net_Off; diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index e6221075d..b423bd149 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1743,7 +1743,8 @@ package body Synth.Vhdl_Oper is return Create_Value_Net (Get_Net (Ctxt, Operand), Create_Res_Bound (Operand)); - when Iir_Predefined_Ieee_1164_Condition_Operator => + when Iir_Predefined_Ieee_1164_Condition_Operator + | Iir_Predefined_Bit_Condition => return Create_Value_Net (Get_Net (Ctxt, Operand), Get_Subtype_Object (Syn_Inst, Get_Type (Imp))); @@ -1846,6 +1847,21 @@ package body Synth.Vhdl_Oper is Res_Typ, False, Expr); end Synth_Find_Bit; + -- Resize ARG to SIZE bits according to IS_SIGNED. + function Synth_Resize (Ctxt : Context_Acc; + Arg : Valtyp; + Size : Width; + Is_Signed : Boolean; + Loc : Node) return Valtyp + is + N : Net; + begin + N := Get_Net (Ctxt, Arg); + N := Build2_Resize (Ctxt, N, Size, Is_Signed, Get_Location (Loc)); + return Create_Value_Net + (N, Create_Vec_Type_By_Length (Size, Logic_Type)); + end Synth_Resize; + function Synth_Dynamic_Predefined_Function_Call (Subprg_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp is @@ -1865,7 +1881,6 @@ package body Synth.Vhdl_Oper is Arg : constant Valtyp := Get_Value (Subprg_Inst, Param1); Size_Vt : Valtyp; Size : Width; - Arg_Net : Net; begin Size_Vt := Get_Value (Subprg_Inst, Param2); Strip_Const (Size_Vt); @@ -1874,11 +1889,7 @@ package body Synth.Vhdl_Oper is return No_Valtyp; end if; Size := Uns32 (Read_Discrete (Size_Vt)); - Arg_Net := Get_Net (Ctxt, Arg); - Arg_Net := Build2_Resize (Ctxt, Arg_Net, Size, Is_Signed, - Get_Location (Expr)); - return Create_Value_Net - (Arg_Net, Create_Vec_Type_By_Length (Size, Logic_Type)); + return Synth_Resize (Ctxt, Arg, Size, Is_Signed, Expr); end Synth_Conv_Vector; L : Valtyp; @@ -1941,6 +1952,12 @@ package body Synth.Vhdl_Oper is when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => return Synth_Conv_Vector (False); + when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns => + declare + B : constant Bound_Type := Get_Array_Bound (R.Typ, 1); + begin + return Synth_Resize (Ctxt, L, B.Len, False, Expr); + end; when Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int => return Synth_Conv_Vector (True); @@ -1992,30 +2009,17 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => - declare - W : Width; - begin - if not Is_Static (R.Val) then - Error_Msg_Synth (+Expr, "size must be constant"); - return No_Valtyp; - end if; - W := Uns32 (Read_Discrete (R)); - return Create_Value_Net - (Build2_Sresize (Ctxt, Get_Net (Ctxt, L), - W, Get_Location (Expr)), - Create_Vec_Type_By_Length (W, Logic_Type)); - end; + if not Is_Static (R.Val) then + Error_Msg_Synth (+Expr, "size must be constant"); + return No_Valtyp; + end if; + return Synth_Resize + (Ctxt, L, Uns32 (Read_Discrete (R)), True, Expr); when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn => declare - B : Bound_Type; - W : Width; + B : constant Bound_Type := Get_Array_Bound (R.Typ, 1); begin - B := Get_Array_Bound (R.Typ, 1); - W := B.Len; - return Create_Value_Net - (Build2_Sresize (Ctxt, Get_Net (Ctxt, L), - W, Get_Location (Expr)), - Create_Vec_Type_By_Length (W, Logic_Type)); + return Synth_Resize (Ctxt, L, B.Len, True, Expr); end; when Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Uns_Nat | Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Sgn_Nat diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index df8a851ce..3d8c7bba2 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -144,14 +144,17 @@ package body Synth.Vhdl_Stmts is declare Voff : Net; Off : Value_Offsets; + Err : Boolean; begin Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Pfx), Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); Strip_Const (Dest_Base); - Synth_Indexed_Name (Syn_Inst, Pfx, Dest_Typ, Voff, Off); + Synth_Indexed_Name (Syn_Inst, Pfx, Dest_Typ, Voff, Off, Err); - if Voff = No_Net then + if Err then + Dest_Base := No_Valtyp; + elsif Voff = No_Net then -- Static index. Dest_Off := Dest_Off + Off; else diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 630f3ef84..9fc9788bf 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -340,8 +340,8 @@ package body Vhdl.Annotations is then -- This subtype has created a new anonymous subtype for the -- element. - Annotate_Type_Definition - (Block_Info, Get_Element_Subtype (Def)); + El := Get_Element_Subtype (Def); + Annotate_Type_Definition (Block_Info, El); end if; if Flag_Synthesis then -- For the bounds. @@ -378,8 +378,23 @@ package body Vhdl.Annotations is when Iir_Kind_Record_Subtype_Definition => if Flag_Synthesis then - -- For the offsets. - Create_Object_Info (Block_Info, Def, Kind_Type); + declare + List : constant Iir_Flist := + Get_Elements_Declaration_List (Def); + El : Iir; + El_Type : Iir; + begin + for I in Flist_First .. Flist_Last (List) loop + El := Get_Nth_Element (List, I); + if Get_Subtype_Indication (El) /= Null_Iir then + El_Type := Get_Type (El); + Annotate_Anonymous_Type_Definition + (Block_Info, El_Type); + end if; + end loop; + -- For the offsets. + Create_Object_Info (Block_Info, Def, Kind_Type); + end; end if; when Iir_Kind_Access_Type_Definition => diff --git a/testsuite/synth/issue1961/bug.vhdl b/testsuite/synth/issue1961/bug.vhdl new file mode 100644 index 000000000..61a3593ed --- /dev/null +++ b/testsuite/synth/issue1961/bug.vhdl @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port ( + clk : in std_ulogic + ); +end bug; + +architecture struct of bug is + + type a_t is record + value : unsigned; + end record; + + type a_array_t is array(natural range<>) of a_t; + + type b_t is record + a : a_array_t; + end record; + + type b_array_t is array(natural range<>) of b_t; + + function fun return natural is + variable b : b_array_t(0 to 1)(a(0 to 31)(value(31 downto 0))); + begin + return 0; + end function; + + constant dummy : natural := fun; +begin + +end architecture; diff --git a/testsuite/synth/issue1961/repro.vhdl b/testsuite/synth/issue1961/repro.vhdl new file mode 100644 index 000000000..4c2f7c290 --- /dev/null +++ b/testsuite/synth/issue1961/repro.vhdl @@ -0,0 +1,30 @@ +entity repro is + port ( + clk : in bit + ); +end; + +architecture struct of repro is + + type a_t is record + value : bit_vector; + end record; + + type a_array_t is array(natural range<>) of a_t; + + type b_t is record + a : a_array_t; + end record; + + type b_array_t is array(natural range<>) of b_t; + + function fun return natural is + variable b : b_array_t(0 to 1)(a(0 to 31)(value(31 downto 0))); + begin + return 0; + end function; + + constant dummy : natural := fun; +begin + +end architecture; diff --git a/testsuite/synth/issue1961/testsuite.sh b/testsuite/synth/issue1961/testsuite.sh new file mode 100755 index 000000000..0fee34170 --- /dev/null +++ b/testsuite/synth/issue1961/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +exit 0 +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue1968/dummy.vhdl b/testsuite/synth/issue1968/dummy.vhdl new file mode 100644 index 000000000..2aa42e172 --- /dev/null +++ b/testsuite/synth/issue1968/dummy.vhdl @@ -0,0 +1,23 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.NUMERIC_STD.all; +use work.dummy_pkg.all; + +entity dummy is + port ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ); +end dummy; + +architecture rtl of dummy is +begin + +-- this_works(A_i, B_i, C_i, o); + + this_doesnt_work(A_i, B_i, C_i, o); + +end rtl; diff --git a/testsuite/synth/issue1968/dummy_pkg.vhdl b/testsuite/synth/issue1968/dummy_pkg.vhdl new file mode 100644 index 000000000..bc9c3244f --- /dev/null +++ b/testsuite/synth/issue1968/dummy_pkg.vhdl @@ -0,0 +1,110 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.NUMERIC_STD.all; + +package dummy_pkg is + type wordarray is array (natural range<>) of std_logic_vector(31 downto 0); + + procedure p_csa ( + variable A: in std_logic_vector(31 downto 0); + variable B: in std_logic_vector(31 downto 0); + variable Ci: in std_logic_vector(31 downto 0); + variable S: out std_logic_vector(31 downto 0); + variable Co: out std_logic_vector(31 downto 0) + ); + + function f_csa ( + A : std_logic_vector(31 downto 0); + B: std_logic_vector(31 downto 0); + Ci: std_logic_vector(31 downto 0) + ) return wordarray; + + procedure this_works ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ); + + procedure this_doesnt_work ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ); + +end dummy_pkg; + +package body dummy_pkg is + + procedure p_csa ( + variable A: in std_logic_vector(31 downto 0); + variable B: in std_logic_vector(31 downto 0); + variable Ci: in std_logic_vector(31 downto 0); + variable S: out std_logic_vector(31 downto 0); + variable Co: out std_logic_vector(31 downto 0) + ) is + variable Co_tmp : std_logic_vector(32 downto 0); + begin + S := A xor B xor Ci; + Co_tmp := ((A and B) or (B and Ci) or (A and Ci)) & '0'; + Co := Co_tmp(31 downto 0); + end procedure p_csa; + + function f_csa ( + A : std_logic_vector(31 downto 0); + B: std_logic_vector(31 downto 0); + Ci: std_logic_vector(31 downto 0) + ) return wordarray is + variable r : wordarray(1 downto 0); + variable Co_tmp : std_logic_vector(32 downto 0); + begin + r(0) := A xor B xor Ci; + Co_tmp := ((A and B) or (B and Ci) or (A and Ci)) & '0'; + r(1) := Co_tmp(31 downto 0); + return r; + end function; + + procedure this_works ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ) is + variable a : std_logic_vector(31 downto 0); + variable b : std_logic_vector(31 downto 0); + variable c : std_logic_vector(31 downto 0); + variable r0 : wordarray(1 downto 0); + variable s0 : std_logic_vector(31 downto 0); + variable c0 : std_logic_vector(31 downto 0); + begin + a := A_i; + b := B_i; + c := C_i; + r0 := f_csa(a, b, c); + s0 := r0(0); + c0 := r0(1); + o <= s0 + c0; + end procedure this_works; + + procedure this_doesnt_work ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ) is + variable a : std_logic_vector(31 downto 0); + variable b : std_logic_vector(31 downto 0); + variable c : std_logic_vector(31 downto 0); + variable s0 : std_logic_vector(31 downto 0); + variable c0 : std_logic_vector(31 downto 0); + begin + a := A_i; + b := B_i; + c := C_i; + p_csa(a, b, c, s0, c0); + o <= s0 + c0; + end procedure this_doesnt_work; + +end dummy_pkg; diff --git a/testsuite/synth/issue1968/testsuite.sh b/testsuite/synth/issue1968/testsuite.sh new file mode 100755 index 000000000..9b5b1ea72 --- /dev/null +++ b/testsuite/synth/issue1968/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth -fsynopsys dummy_pkg.vhdl dummy.vhdl -e > syn_dummy.vhdl + +echo "Test successful" diff --git a/testsuite/synth/issue1971/repro_bit_oper.vhdl b/testsuite/synth/issue1971/repro_bit_oper.vhdl new file mode 100644 index 000000000..d5daa14cc --- /dev/null +++ b/testsuite/synth/issue1971/repro_bit_oper.vhdl @@ -0,0 +1,8 @@ +entity repro_bit_oper is + port (x : in bit; y : out boolean); +end; + +architecture a of repro_bit_oper is +begin + y <= true when x else false; +end; diff --git a/testsuite/synth/issue1971/testsuite.sh b/testsuite/synth/issue1971/testsuite.sh new file mode 100755 index 000000000..61a429361 --- /dev/null +++ b/testsuite/synth/issue1971/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only repro_bit_oper + +echo "Test successful" diff --git a/testsuite/synth/issue1972/ent.vhdl b/testsuite/synth/issue1972/ent.vhdl new file mode 100644 index 000000000..502f47785 --- /dev/null +++ b/testsuite/synth/issue1972/ent.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port (output : out std_ulogic); +end entity; + +architecture rtl of ent is + signal sr : std_ulogic_vector(0 downto 1); +begin + output <= sr(1); +end architecture; diff --git a/testsuite/synth/issue1972/testsuite.sh b/testsuite/synth/issue1972/testsuite.sh new file mode 100755 index 000000000..f6f8ea08f --- /dev/null +++ b/testsuite/synth/issue1972/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_failure ent.vhdl -e + +echo "Test successful" diff --git a/testsuite/synth/issue1977/testsuite.sh b/testsuite/synth/issue1977/testsuite.sh new file mode 100755 index 000000000..665792ea1 --- /dev/null +++ b/testsuite/synth/issue1977/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only triangularcounter + +echo "Test successful" diff --git a/testsuite/synth/issue1977/triangularcounter.vhdl b/testsuite/synth/issue1977/triangularcounter.vhdl new file mode 100644 index 000000000..c1851de19 --- /dev/null +++ b/testsuite/synth/issue1977/triangularcounter.vhdl @@ -0,0 +1,48 @@ +library IEEE; +context IEEE.IEEE_std_context; + +entity TriangularCounter is + generic ( + g_Precision : natural := 11 + ); + port ( + CLK : in std_logic; + RST : in std_logic; + EN : in std_logic; + REF : out unsigned(g_Precision-1 downto 0); + TRIGGER : out std_logic + ); +end entity; + +architecture arch of TriangularCounter is + + signal dir : std_logic; + signal cnt : unsigned(REF'range); + signal tg_max : std_logic; + signal tg_min : std_logic; + +begin + + process(RST, CLK) + begin + if RST then + cnt <= (others=>'0'); + dir <= '0'; + elsif rising_edge(CLK) then + if EN then + cnt <= cnt-1 when dir else cnt+1; + if tg_min or tg_max then + dir <= not dir; + end if; + end if; + end if; + end process; + + tg_max <= (not dir) and (cnt ?= to_unsigned(2**g_Precision-2, REF)); + tg_min <= dir and (cnt ?= 1); + + REF <= cnt; + TRIGGER <= tg_min; + +end architecture; + diff --git a/testsuite/synth/issue1978/reproducer.vhdl b/testsuite/synth/issue1978/reproducer.vhdl new file mode 100644 index 000000000..38091541b --- /dev/null +++ b/testsuite/synth/issue1978/reproducer.vhdl @@ -0,0 +1,45 @@ +--:file: Entity.vhd + +library IEEE; +context IEEE.IEEE_std_context; + +entity Reproducer is + generic ( + g_Precision : natural := 11; + g_PulsesPerRevolution : natural := 1000 + ); + port ( + CLK : in std_logic; + RST : in std_logic; + EN : in std_logic; + Z : in std_logic; + POS : out unsigned(g_Precision-1 downto 0) + ); +end entity; + +architecture arch of Reproducer is + + signal Position : unsigned(POS'range); + + signal Direction : std_logic := '0'; + +begin + + PositionCounter: process(RST, Z, CLK) + constant CountLimit : unsigned(Position'range) := to_unsigned(4*g_PulsesPerRevolution-1, Position); + begin + if RST or Z then + Position <= (others => '0'); + elsif rising_edge(CLK) and EN='1' then + Position <= + (others=>'0') when Position = CountLimit and Direction='1' else + CountLimit when Position = 0 and Direction='0' else + Position+1 when Direction else + Position-1; + end if; + end process; + + pos <= position; + direction <= '0'; + +end architecture; diff --git a/testsuite/synth/issue1978/testsuite.sh b/testsuite/synth/issue1978/testsuite.sh new file mode 100755 index 000000000..6755c8a4e --- /dev/null +++ b/testsuite/synth/issue1978/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_failure reproducer.vhdl -e + +echo "Test successful" |