diff options
| -rw-r--r-- | src/grt/grt-signals.ads | 3 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 20 |
2 files changed, 7 insertions, 16 deletions
diff --git a/src/grt/grt-signals.ads b/src/grt/grt-signals.ads index 896646f37..618ec8805 100644 --- a/src/grt/grt-signals.ads +++ b/src/grt/grt-signals.ads @@ -608,6 +608,9 @@ package Grt.Signals is Val : Value_Union; After : Std_Time); + procedure Ghdl_Process_Add_Port_Driver + (Sign : Ghdl_Signal_Ptr; Val : Value_Union); + -- For B1 function Ghdl_Create_Signal_B1 (Val_Ptr : Ghdl_Value_Ptr; Resolv_Func : Resolver_Acc; diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 70305d04f..e37c4aa7e 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -246,22 +246,10 @@ package body Simul.Vhdl_Simul is begin case Typ.Kind is when Type_Logic - | Type_Bit => - Grt.Signals.Ghdl_Signal_Add_Port_Driver_E8 - (Read_Sig (Sig), Read_U8 (Val)); - when Type_Discrete => - if Typ.Sz = 1 then - Grt.Signals.Ghdl_Signal_Add_Port_Driver_E8 - (Read_Sig (Sig), Read_U8 (Val)); - elsif Typ.Sz = 4 then - Grt.Signals.Ghdl_Signal_Add_Port_Driver_I32 - (Read_Sig (Sig), Read_I32 (Val)); - elsif Typ.Sz = 8 then - Grt.Signals.Ghdl_Signal_Add_Port_Driver_I64 - (Read_Sig (Sig), Read_I64 (Val)); - else - raise Internal_Error; - end if; + | Type_Bit + | Type_Discrete => + Grt.Signals.Ghdl_Process_Add_Port_Driver + (Read_Sig (Sig), To_Ghdl_Value ((Typ, Val))); when Type_Vector | Type_Array => declare |