diff options
| -rw-r--r-- | pyGHDL/dom/Aggregates.py | 21 | ||||
| -rw-r--r-- | pyGHDL/dom/formatting/prettyprint.py | 17 | ||||
| -rw-r--r-- | testsuite/pyunit/SimpleEntity.vhdl | 2 |
3 files changed, 27 insertions, 13 deletions
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py index 5a77b7e37..89acfa312 100644 --- a/pyGHDL/dom/Aggregates.py +++ b/pyGHDL/dom/Aggregates.py @@ -41,6 +41,8 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E """ from pydecor import export +from pyGHDL.dom.Range import Range +from pyGHDL.dom.Symbol import EnumerationLiteralSymbol from pyVHDLModel.VHDLModel import ( SimpleAggregateElement as VHDLModel_SimpleAggregateElement, IndexedAggregateElement as VHDLModel_IndexedAggregateElement, @@ -63,19 +65,30 @@ class SimpleAggregateElement(VHDLModel_SimpleAggregateElement): @export class IndexedAggregateElement(VHDLModel_IndexedAggregateElement): - pass + def __init__(self, index: Expression, expression: Expression): + super().__init__() + self._index = index + self._expression = expression @export class RangedAggregateElement(VHDLModel_RangedAggregateElement): - pass + def __init__(self, r: Range, expression: Expression): + super().__init__() + self._range = r + self._expression = expression @export class NamedAggregateElement(VHDLModel_NamedAggregateElement): - pass + def __init__(self, name: EnumerationLiteralSymbol, expression: Expression): + super().__init__() + self._name = name + self._expression = expression @export class OthersAggregateElement(VHDLModel_OthersAggregateElement): - pass + def __init__(self, expression: Expression): + super().__init__() + self._expression = expression diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 1167d41f4..a2ad6e949 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -4,6 +4,7 @@ from pydecor import export from pyGHDL.dom.Aggregates import SimpleAggregateElement, IndexedAggregateElement, RangedAggregateElement, NamedAggregateElement, OthersAggregateElement from pyGHDL.dom.Object import Constant, Signal +from pyGHDL.dom.Range import Range from pyVHDLModel.VHDLModel import ( GenericInterfaceItem, Expression, @@ -322,14 +323,7 @@ class PrettyPrint: return "{type}".format(type=subTypeIndication.SymbolName) elif isinstance(subTypeIndication, ConstrainedSubTypeSymbol): constraints = ", ".join( - [ - "{left} {dir} {right}".format( - left=self.formatExpression(constraint.Range.LeftBound), - right=self.formatExpression(constraint.Range.RightBound), - dir=DirectionTranslation[constraint.Range.Direction], - ) - for constraint in subTypeIndication.Constraints - ] + [self.formatRange(constraint.Range) for constraint in subTypeIndication.Constraints] ) return "{type}({constraints})".format( @@ -348,6 +342,13 @@ class PrettyPrint: return " := {expr}".format(expr=self.formatExpression(item.DefaultExpression)) + def formatRange(self, r: Range) -> str: + return "{left} {dir} {right}".format( + left=self.formatExpression(r.LeftBound), + right=self.formatExpression(r.RightBound), + dir=DirectionTranslation[r.Direction], + ) + def formatExpression(self, expression: Expression) -> str: if isinstance(expression, SimpleObjectSymbol): return "{name}".format(name=expression.SymbolName) diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl index 8d5b034bb..12068c06d 100644 --- a/testsuite/pyunit/SimpleEntity.vhdl +++ b/testsuite/pyunit/SimpleEntity.vhdl @@ -29,7 +29,7 @@ begin end architecture behav; package package_1 is - constant ghdl : float := (3, 5); -- 2.3; + constant ghdl : float := (3, 5, 0 => 5, 3 => 4, name => 10); -- 2.3; end package; package body package_1 is |