diff options
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 9 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-canon.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 4 | ||||
| -rw-r--r-- | testsuite/synth/psl02/assert2.vhdl | 4 | ||||
| -rwxr-xr-x | testsuite/synth/psl02/testsuite.sh | 5 | ||||
| -rw-r--r-- | testsuite/synth/psl02/verif5.vhdl | 23 |
9 files changed, 55 insertions, 8 deletions
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index e5fc5e97b..4a1eb7331 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -374,7 +374,9 @@ package body Elab.Vhdl_Insts is | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Attribute_Specification + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration => Elab_Declaration (Unit_Inst, Item, Last_Type); when Iir_Kinds_Concurrent_Signal_Assignment | Iir_Kinds_Process_Statement @@ -384,7 +386,7 @@ package body Elab.Vhdl_Insts is | Iir_Kind_Component_Instantiation_Statement => Elab_Concurrent_Statement (Unit_Inst, Item); when others => - Error_Kind ("elab_vunit_declaration", Item); + Error_Kind ("elab_verification_unit", Item); end case; Item := Get_Chain (Item); end loop; diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 2717d5eec..0d8899465 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -858,6 +858,7 @@ package body Synth.Vhdl_Expr is | Iir_Kind_Constant_Declaration | Iir_Kind_Iterator_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Interface_File_Declaration => return Get_Value (Syn_Inst, Name); @@ -2162,7 +2163,8 @@ package body Synth.Vhdl_Expr is | Iir_Kind_Selected_Name | Iir_Kind_Interface_Signal_Declaration -- For PSL. | Iir_Kind_Signal_Declaration -- For PSL. - | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Object_Alias_Declaration -- For PSL + | Iir_Kind_Non_Object_Alias_Declaration -- For PSL | Iir_Kind_Implicit_Dereference | Iir_Kind_Dereference => declare diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 989942244..d26b24f73 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -117,6 +117,7 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Constant_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Object_Alias_Declaration => declare Targ : constant Valtyp := Get_Value (Syn_Inst, Pfx); @@ -3785,7 +3786,9 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Attribute_Specification + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration => Synth_Concurrent_Declaration (Syn_Inst, Item); when Iir_Kinds_Concurrent_Signal_Assignment | Iir_Kinds_Process_Statement @@ -3827,7 +3830,9 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Attribute_Specification + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration => Finalize_Declaration (Syn_Inst, Item, False); when others => Error_Kind ("synth_verification_unit(2)", Item); diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 9daa19abc..a1d8c7611 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1167,7 +1167,9 @@ package body Vhdl.Annotations is | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Attribute_Specification + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration => Annotate_Declaration (Vunit_Info, Item); when Iir_Kinds_Concurrent_Signal_Assignment | Iir_Kinds_Process_Statement diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index ddaed3792..aba586eae 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -3433,7 +3433,9 @@ package body Vhdl.Canon is | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Attribute_Specification + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration => Item := Canon_Declaration (Unit, Item, Null_Iir); when Iir_Kinds_Concurrent_Signal_Assignment | Iir_Kinds_Process_Statement diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index c000c1a47..058d4a393 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -1190,7 +1190,9 @@ package body Vhdl.Sem_Psl is | Iir_Kind_Function_Body | Iir_Kind_Procedure_Body | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Attribute_Specification + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration => Sem_Decls.Sem_Declaration (Item, Prev_Item, False, Attr_Spec_Chain); when Iir_Kinds_Concurrent_Signal_Assignment diff --git a/testsuite/synth/psl02/assert2.vhdl b/testsuite/synth/psl02/assert2.vhdl index 0286470c8..9b5c351f7 100644 --- a/testsuite/synth/psl02/assert2.vhdl +++ b/testsuite/synth/psl02/assert2.vhdl @@ -9,6 +9,10 @@ end assert2; architecture behav of assert2 is signal val : unsigned (3 downto 0); + function incr (a : integer) return integer is + begin + return a + 1; + end function incr; begin process(clk) begin diff --git a/testsuite/synth/psl02/testsuite.sh b/testsuite/synth/psl02/testsuite.sh index 76b8c58eb..a45a0e0ff 100755 --- a/testsuite/synth/psl02/testsuite.sh +++ b/testsuite/synth/psl02/testsuite.sh @@ -27,4 +27,9 @@ analyze syn_assert23.vhdl clean +synth assert2.vhdl verif5.vhdl -e assert2 > syn_assert25.vhdl +analyze syn_assert25.vhdl + +clean + echo "Test successful" diff --git a/testsuite/synth/psl02/verif5.vhdl b/testsuite/synth/psl02/verif5.vhdl new file mode 100644 index 000000000..c4d8c02e0 --- /dev/null +++ b/testsuite/synth/psl02/verif5.vhdl @@ -0,0 +1,23 @@ +vunit verif5 (assert2(behav)) +{ + signal cnti : natural; + + -- Aliases to objects + alias cnti_a is cnti; + alias clk_a is clk; + alias rst_a is rst; + alias cnt_a is cnt; + + -- Alias to non-object + alias incr_a is incr[integer return integer]; + + cnti_a <= to_integer(cnt); + + default clock is rising_edge(clk_a); + + assert always cnt_a /= 5 abort rst_a; + assert always rst_a = rst; + assert always cnt_a = cnt; + assert always cnti_a = cnt; + assert always cnti_a = incr_a(prev(cnti_a)); +} |