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diff --git a/doc/using/Synthesis.rst b/doc/using/Synthesis.rst new file mode 100644 index 000000000..c236152e6 --- /dev/null +++ b/doc/using/Synthesis.rst @@ -0,0 +1,67 @@ +.. program:: ghdl +.. _USING:Synthesis: + +Synthesis +######### + +.. WARNING:: + This is experimental and work in progress! If you find crashes or unsupported features, please :ref:`report them <reporting_bugs>`! + +Since ``v0.37``, GHDL features a built-in (experimental) synthesis kernel with two backends: ``synth`` and ``yosys-plugin``. Currently, synthesis is supported as a front-end of other synthesis and technology mapping tools. +Hence, the netlists generated by GHDL are not optimised. + +.. NOTE:: + Due to GHDL's modular architecture (see :ref:`INT:Overview`), the synthesis kernel shares the VHDL parsing front-end with the simulation back-ends. Hence, available options for synthesis are the same as for analysis and/or simulation elaboration (see :ref:`GHDL:options`). + +.. index:: synthesis command + +.. _Synth:command: + +Synthesis [``--synth``] +======================= + +.. HINT:: + This command is useful for checking that a design can be synthesized, before actually running a complete synthesis + tool. In fact, because this is expected to be much faster, it can be used as a frequent check. + +.. TIP:: + Since GHDL's front-end supports multiple versions of the standard, but the synthesised netlists are generated using + a subset of VHDL 1993, GHDL's synthesis features can be used as a preprocessor with tools that do support older + versions of the standard, but which don't provide the most recent features. + +.. option:: --synth <[options] primary_unit [secondary_unit]> + +Elaborates for synthesis the design whose top unit is indicated by ``primary_unit [secondary_unit]``. + +.. ATTENTION:: + All the units must have been analyzed; that is, the artifacts of previously executed :option:`-a` calls must exist. + +.. option:: --synth <[options] files... -e primary_unit [secondary_unit]> + +Analyses and elaborates for synthesis the files present on the command line only. +Elaboration starts from the top unit indicated by ``primary_unit [secondary_unit]``. + +Currently, the output is a generic netlist using a (very simple) subset of VHDL 1993. +See :ghdlsharp:`1174` for on-going discussion about other output formats. + +.. TIP:: + Files can be provided in any order. + +.. _Synth:plugin: + +Yosys plugin +============ + +`ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`_ is a module to use GHDL as a VHDL front-end for `Yosys +Open Synthesis Suite <http://www.clifford.at/yosys/>`_, a framework for optimised synthesis and technology mapping. +Artifacts generated by Yosys can be used in multiple open source and vendor tools to achieve P&R, formal verification, +etc. A relevant feature of combining GHDL and Yosys is that mixed-language (VHDL-Verilog) synthesis with open source +tools is possible. + +The command line syntax for this plugin is the same as for :option:``--synth``, except that the command name (``--synth``) +is neither required nor supported. Instead, ``yosys``, ``yosys -m ghdl`` or ``yosys -m path/to/ghdl.so`` need to be used, +depending of how is the plugin built. See `README <https://github.com/ghdl/ghdl-yosys-plugin>`_ for building and installation +guidelines. + +.. HINT:: + ghdl-yosys-plugin is a thin layer that converts the internal representation of :option:`--synth` to Yosys' C API. Hence, it is suggested to check the designs with :option:`--synth` before running synthesis with Yosys. |