diff options
Diffstat (limited to 'libraries/openieee/build_numeric.py')
| -rwxr-xr-x | libraries/openieee/build_numeric.py | 606 |
1 files changed, 375 insertions, 231 deletions
diff --git a/libraries/openieee/build_numeric.py b/libraries/openieee/build_numeric.py index df6c8515f..53700dc42 100755 --- a/libraries/openieee/build_numeric.py +++ b/libraries/openieee/build_numeric.py @@ -21,40 +21,44 @@ # along with GHDL; see the file COPYING.md. If not see # <http://www.gnu.org/licenses/>. -import re import sys # My python 'style' and knowledge is basic... Do not hesitate to comment. -binary_funcs = [ "and", "nand", "or", "nor", "xor" ] -compare_funcs = [ "=", "/=", ">", ">=", "<", "<=" ] +binary_funcs = ["and", "nand", "or", "nor", "xor"] +compare_funcs = ["=", "/=", ">", ">=", "<", "<="] -vec_types = ['UNSIGNED', 'SIGNED'] +vec_types = ["UNSIGNED", "SIGNED"] -logics = ['bit', 'std'] -logic_types = {'bit' : 'bit', 'std': 'sl_x01' } -logic_undefs = {'bit' : "'0'", 'std': "'X'" } +logics = ["bit", "std"] +logic_types = {"bit": "bit", "std": "sl_x01"} +logic_undefs = {"bit": "'0'", "std": "'X'"} -logic = 'xx' # Current logic, either bit or std +logic = "xx" # Current logic, either bit or std -v93=False +v93 = False # Stream to write. -out=sys.stdout +out = sys.stdout + def w(s): - "Write S to the output" + """Write S to the output.""" out.write(s) + def logic_type(): return logic_types[logic] + def logic_undef(): return logic_undefs[logic] + def disp_vec_binary(func, typ): - "Generate the body of a vector binary logic function" - res = """ + """Generate the body of a vector binary logic function.""" + res = ( + """ function "{0}" (l, r : {1}) return {1} is subtype res_type is {1} (l'length - 1 downto 0); @@ -66,7 +70,9 @@ def disp_vec_binary(func, typ): assert false report "NUMERIC_STD.""{0}"": arguments are not of the same length" severity failure; - res := (others => """ + logic_undef() + """); + res := (others => """ + + logic_undef() + + """); else for I in res_type'range loop res (I) := la (I) {0} ra (I); @@ -74,49 +80,63 @@ def disp_vec_binary(func, typ): end if; return res; end "{0}";\n""" - w (res.format(func, typ)) + ) + w(res.format(func, typ)) + def disp_non_logical_warning(func): return """ assert NO_WARNING report "NUMERIC_STD.""{0}"": non logical value detected" - severity warning;""".format(func) + severity warning;""".format( + func + ) + def conv_bit(expr): - if logic == 'std': + if logic == "std": return "sl_to_x01 (" + expr + ")" else: return expr + def extract_bit(name): - res = "{0}b := " + conv_bit ("{0}a (i)") + ";" + res = "{0}b := " + conv_bit("{0}a (i)") + ";" return res.format(name) + def init_carry(func): - if func == '+': + if func == "+": return """ carry := '0';""" else: return """ carry := '1';""" -def extract_extend_bit(name,typ): + +def extract_extend_bit(name, typ): res = """ if i > {0}a'left then {0}b := """ - if typ == 'UNSIGNED': + if typ == "UNSIGNED": res += "'0';" else: res += "{0} ({0}'left);" - res += """ + res += ( + """ else - """ + extract_bit(name) + """ + """ + + extract_bit(name) + + """ end if;""" + ) return res.format(name) + def disp_vec_vec_binary(func, typ): - "Generate vector binary function body" - res = """ + """Generate vector binary function body.""" + res = ( + """ function "{0}" (l, r : {1}) return {1} is constant lft : integer := MAX (l'length, r'length) - 1; @@ -124,27 +144,33 @@ def disp_vec_vec_binary(func, typ): alias la : {1} (l'length - 1 downto 0) is l; alias ra : {1} (r'length - 1 downto 0) is r; variable res : res_type; - variable lb, rb, carry : """ + logic_type () + """; + variable lb, rb, carry : """ + + logic_type() + + """; begin if la'left < 0 or ra'left < 0 then return null_{1}; end if;""" + ) res += init_carry(func) res += """ for i in 0 to lft loop""" - res += extract_extend_bit('l', typ) - res += extract_extend_bit('r', typ) - - if logic == 'std': - res += """ - if lb = 'X' or rb = 'X' then""" + \ - disp_non_logical_warning(func) + """ + res += extract_extend_bit("l", typ) + res += extract_extend_bit("r", typ) + + if logic == "std": + res += ( + """ + if lb = 'X' or rb = 'X' then""" + + disp_non_logical_warning(func) + + """ res := (others => 'X'); exit; end if;""" - if func == '-': + ) + if func == "-": res += """ rb := not rb;""" res += """ @@ -154,20 +180,25 @@ def disp_vec_vec_binary(func, typ): return res; end "{0}"; """ - w (res.format (func, typ)) + w(res.format(func, typ)) + def declare_int_var(name, typ): res = """ variable {0}1, {0}2 : {1}; - variable {0}d : nat1;"""; + variable {0}d : nat1;""" if typ == "INTEGER": res += """ constant {0}msb : nat1 := boolean'pos({0} < 0);""" return res.format(name, typ) + def init_int_var(name, typ): return """ - {0}1 := {0};""".format(name); + {0}1 := {0};""".format( + name + ) + def extract_int_lsb(name, typ): res = """ @@ -187,7 +218,8 @@ def extract_int_lsb(name, typ): {0}1 := {0}2;""" res += """ {0}b := nat1_to_01 ({0}d);""" - return res.format(name,typ) + return res.format(name, typ) + def check_int_truncated(func, name, typ): if typ == "INTEGER": @@ -199,92 +231,109 @@ def check_int_truncated(func, name, typ): assert NO_WARNING report "NUMERIC_STD.""{0}"": vector is truncated" severity warning; - end if;""".format(func, name, v) + end if;""".format( + func, name, v + ) + def create_vec_int_dict(func, left, right): if left in vec_types: - dic = {'vtype': left, - 'itype': right, - 'vparam': 'l', - 'iparam': 'r'} + dic = {"vtype": left, "itype": right, "vparam": "l", "iparam": "r"} else: - dic = {'vtype': right, - 'itype': left, - 'vparam': 'r', - 'iparam': 'l'} - dic.update({'ltype': left, - 'rtype': right, - 'func': func, - 'logic': logic_type()}) + dic = {"vtype": right, "itype": left, "vparam": "r", "iparam": "l"} + dic.update({"ltype": left, "rtype": right, "func": func, "logic": logic_type()}) return dic + def disp_vec_int_binary(func, left, right): - "Generate vector binary function body" + """Generate vector binary function body.""" dic = create_vec_int_dict(func, left, right) - res = """ + res = ( + """ function "{func}" (l : {ltype}; r : {rtype}) return {vtype} is subtype res_type is {vtype} ({vparam}'length - 1 downto 0); - alias {vparam}a : res_type is {vparam};""" + \ - declare_int_var (dic["iparam"], dic["itype"]) + """ + alias {vparam}a : res_type is {vparam};""" + + declare_int_var(dic["iparam"], dic["itype"]) + + """ variable res : res_type; variable lb, rb, carry : {logic}; begin if res'length < 0 then return null_{vtype}; end if;""" + ) # Initialize carry. For subtraction, use 2-complement. res += init_carry(func) - res += init_int_var(dic['iparam'], dic['itype']) + """ + res += ( + init_int_var(dic["iparam"], dic["itype"]) + + """ for i in res'reverse_range loop - """ + extract_bit(dic['vparam']) + "\n" + \ - extract_int_lsb(dic['iparam'], dic['itype']); - - if logic == 'std': - res += """ - if {vparam}b = 'X' then""" + \ - disp_non_logical_warning(func) + """ + """ + + extract_bit(dic["vparam"]) + + "\n" + + extract_int_lsb(dic["iparam"], dic["itype"]) + ) + + if logic == "std": + res += ( + """ + if {vparam}b = 'X' then""" + + disp_non_logical_warning(func) + + """ res := (others => 'X'); {iparam}1 := 0; exit; end if;""" + ) # 2-complement for subtraction - if func == '-': + if func == "-": res += """ rb := not rb;""" - res += """ + res += ( + """ res (i) := compute_sum (carry, rb, lb); carry := compute_carry (carry, rb, lb); - end loop;""" + \ - check_int_truncated(func, dic['iparam'], dic['itype']) + """ + end loop;""" + + check_int_truncated(func, dic["iparam"], dic["itype"]) + + """ return res; end "{func}";\n""" - w(res.format (**dic)) + ) + w(res.format(**dic)) + def disp_vec_int_gcompare(func, left, right): - "Generate comparison function" + """Generate comparison function.""" dic = create_vec_int_dict(func, left, right) - res = """ + res = ( + """ function {func} (l : {ltype}; r : {rtype}) return compare_type is subtype res_type is {vtype} ({vparam}'length - 1 downto 0); - alias la : res_type is l;""" + \ - declare_int_var (dic['iparam'], dic['itype']) + """ + alias la : res_type is l;""" + + declare_int_var(dic["iparam"], dic["itype"]) + + """ variable lb, rb : {logic}; variable res : compare_type; begin - res := compare_eq;"""; + res := compare_eq;""" + ) - res += init_int_var(dic['iparam'], dic['itype']) + """ + res += ( + init_int_var(dic["iparam"], dic["itype"]) + + """ for i in {vparam}a'reverse_range loop - """ + extract_bit (dic['vparam']) + \ - extract_int_lsb("r", right) + """ + + extract_bit(dic["vparam"]) + + extract_int_lsb("r", right) + ) - if logic == 'std': + if logic == "std": res += """ if {vparam}b = 'X' then return compare_unknown; @@ -303,8 +352,11 @@ def disp_vec_int_gcompare(func, left, right): res := compare_lt; end if;""" else: - res += """ - if """ + conv_bit ("l (l'left)") + """ = '1' then + res += ( + """ + if """ + + conv_bit("l (l'left)") + + """ = '1' then if r >= 0 then res := compare_lt; end if; @@ -313,21 +365,25 @@ def disp_vec_int_gcompare(func, left, right): res := compare_gt; end if; end if;""" + ) res += """ return res; end {func}; """ - w(res.format (**dic)) + w(res.format(**dic)) + def disp_vec_int_compare(func, left, right): - "Generate comparison function" + """Generate comparison function.""" dic = create_vec_int_dict(func, left, right) - res = """ + res = ( + """ function "{func}" (l : {ltype}; r : {rtype}) return boolean is subtype res_type is {vtype} ({vparam}'length - 1 downto 0); - alias {vparam}a : res_type is {vparam};""" + \ - declare_int_var (dic['iparam'], dic['itype']) + """ + alias {vparam}a : res_type is {vparam};""" + + declare_int_var(dic["iparam"], dic["itype"]) + + """ variable res : compare_type; begin if {vparam}'length = 0 then @@ -338,6 +394,7 @@ def disp_vec_int_compare(func, left, right): end if; res := """ + ) if left == "SIGNED" or right == "SIGNED": res += "scompare" @@ -347,12 +404,15 @@ def disp_vec_int_compare(func, left, right): res += " (l, r);" else: res += " (r, l);" - if logic == 'std': - res += """ - if res = compare_unknown then""" + \ - disp_non_logical_warning(func) + """ + if logic == "std": + res += ( + """ + if res = compare_unknown then""" + + disp_non_logical_warning(func) + + """ return false; end if;""" + ) if left in vec_types: res += """ @@ -363,10 +423,11 @@ def disp_vec_int_compare(func, left, right): res += """ end "{func}"; """ - w(res.format (**dic)) + w(res.format(**dic)) + def disp_vec_vec_gcompare(func, typ): - "Generate comparison function" + """Generate comparison function.""" res = """ function {func} (l, r : {typ}) return compare_type is @@ -376,11 +437,16 @@ def disp_vec_vec_gcompare(func, typ): variable lb, rb : {logic}; variable res : compare_type; begin""" - if typ == 'SIGNED': - res += """ + if typ == "SIGNED": + res += ( + """ -- Consider sign bit as S * -(2**N). - lb := """ + conv_bit ("la (la'left)") + """; - rb := """ + conv_bit ("ra (ra'left)") + """; + lb := """ + + conv_bit("la (la'left)") + + """; + rb := """ + + conv_bit("ra (ra'left)") + + """; if lb = '1' and rb = '0' then return compare_lt; elsif lb = '0' and rb = '1' then @@ -388,18 +454,19 @@ def disp_vec_vec_gcompare(func, typ): else res := compare_eq; end if;""" + ) else: res += """ res := compare_eq;""" - if typ == 'SIGNED': + if typ == "SIGNED": res += """ for i in 0 to sz - 1 loop""" else: res += """ for i in 0 to sz loop""" - res += extract_extend_bit('l', typ) - res += extract_extend_bit('r', typ) - if logic == 'std': + res += extract_extend_bit("l", typ) + res += extract_extend_bit("r", typ) + if logic == "std": res += """ if lb = 'X' or rb = 'X' then return compare_unknown; @@ -415,10 +482,11 @@ def disp_vec_vec_gcompare(func, typ): return res; end {func};\n""" - w(res.format (func=func, typ=typ, logic=logic_type())) + w(res.format(func=func, typ=typ, logic=logic_type())) + def disp_vec_vec_compare(func, typ): - "Generate comparison function" + """Generate comparison function.""" res = """ function "{func}" (l, r : {typ}) return boolean is @@ -438,21 +506,26 @@ def disp_vec_vec_compare(func, typ): res += "ucompare" res += """ (l, r);""" - if logic == 'std': - res += """ - if res = compare_unknown then""" + \ - disp_non_logical_warning(func) + """ + if logic == "std": + res += ( + """ + if res = compare_unknown then""" + + disp_non_logical_warning(func) + + """ return false; end if;""" + ) res += """ return res {func} compare_eq; end "{func}";\n""" - w(res.format (func=func, typ=typ)) + w(res.format(func=func, typ=typ)) + def disp_vec_not(typ): - "Generate vector binary function body" - w(""" + """Generate vector binary function body.""" + w( + """ function "not" (l : {0}) return {0} is subtype res_type is {0} (l'length - 1 downto 0); @@ -463,7 +536,11 @@ def disp_vec_not(typ): res (I) := not la (I); end loop; return res; - end "not";\n""".format(typ)) + end "not";\n""".format( + typ + ) + ) + def disp_resize(typ): res = """ @@ -480,7 +557,7 @@ def disp_resize(typ): end if; if arg1'length > new_size then -- Reduction.""" - if typ == 'SIGNED': + if typ == "SIGNED": res += """ res (res'left) := arg1 (arg1'left); res (res'left - 1 downto 0) := arg1 (res'left - 1 downto 0);""" @@ -491,7 +568,7 @@ def disp_resize(typ): else -- Expansion res (arg1'range) := arg1;""" - if typ == 'SIGNED': + if typ == "SIGNED": res += """ res (res'left downto arg1'length) := (others => arg1 (arg1'left));""" res += """ @@ -500,8 +577,9 @@ def disp_resize(typ): end resize;\n""" w(res.format(typ)) + def gen_shift(dir, inv): - if (dir == 'left') ^ inv: + if (dir == "left") ^ inv: res = """ res (res'left downto {opp}count) := arg1 (arg1'left {sub} count downto 0);""" else: @@ -512,6 +590,7 @@ def gen_shift(dir, inv): else: return res.format(opp="", sub="-") + def disp_shift_op(name, typ, dir): res = """ function {0} (ARG : {1}; COUNT: INTEGER) return {1} @@ -534,6 +613,7 @@ def disp_shift_op(name, typ, dir): end {0};\n""" w(res.format(name, typ)) + def disp_shift(name, typ, dir): res = """ function {0} (ARG : {1}; COUNT: NATURAL) return {1} @@ -541,7 +621,7 @@ def disp_shift(name, typ, dir): subtype res_type is {1} (ARG'length - 1 downto 0); alias arg1 : res_type is arg; variable res : res_type := (others => """ - if typ == 'SIGNED' and dir == 'right': + if typ == "SIGNED" and dir == "right": res += "arg1 (arg1'left)" else: res += "'0'" @@ -558,14 +638,16 @@ def disp_shift(name, typ, dir): end {0};\n""" w(res.format(name, typ)) + def disp_rotate(name, typ, dir): - if 'rotate' in name: - count_type = 'natural' - op = 'rem' + if "rotate" in name: + count_type = "natural" + op = "rem" else: - count_type = 'integer' - op = 'mod' - res = """ + count_type = "integer" + op = "mod" + res = ( + """ function {0} (ARG : {1}; COUNT: {2}) return {1} is subtype res_type is {1} (ARG'length - 1 downto 0); @@ -576,8 +658,11 @@ def disp_rotate(name, typ, dir): if res'length = 0 then return null_{1}; end if; - cnt := count """ + op + " res'length;" - if dir == 'left': + cnt := count """ + + op + + " res'length;" + ) + if dir == "left": res += """ res (res'left downto cnt) := arg1 (res'left - cnt downto 0); res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);""" @@ -590,24 +675,32 @@ def disp_rotate(name, typ, dir): end {0};\n""" w(res.format(name, typ, count_type)) + def disp_vec_vec_mul(func, typ): - res = """ + res = ( + """ function "{0}" (L, R : {1}) return {1} is alias la : {1} (L'Length - 1 downto 0) is l; alias ra : {1} (R'Length - 1 downto 0) is r; variable res : {1} (L'length + R'Length -1 downto 0) := (others => '0'); - variable rb, lb, vb, carry : """ + logic_type() + """; + variable rb, lb, vb, carry : """ + + logic_type() + + """; begin if la'length = 0 or ra'length = 0 then return null_{1}; end if; -- Shift and add L. for i in natural range 0 to ra'left """ - if typ == 'SIGNED': + ) + if typ == "SIGNED": res += "- 1 " - res += """loop - """ + extract_bit ('r') + """ + res += ( + """loop + """ + + extract_bit("r") + + """ if rb = '1' then -- Compute res := res + shift_left (l, i). carry := '0'; @@ -617,7 +710,8 @@ def disp_vec_vec_mul(func, typ): res (i + j) := compute_sum (carry, vb, lb); carry := compute_carry (carry, vb, lb); end loop;""" - if typ == 'UNSIGNED': + ) + if typ == "UNSIGNED": res += """ -- Propagate carry. for j in i + la'length to res'left loop @@ -635,14 +729,15 @@ def disp_vec_vec_mul(func, typ): res (j) := compute_sum (carry, vb, lb); carry := compute_carry (carry, vb, lb); end loop;""" - if logic == 'std': + if logic == "std": res += """ - elsif rb = 'X' then""" + \ - disp_non_logical_warning (func) + elsif rb = 'X' then""" + disp_non_logical_warning( + func + ) res += """ end if; end loop;""" - if typ == 'SIGNED': + if typ == "SIGNED": res += """ if ra (ra'left) = '1' then -- R is a negative number. It is considered as: @@ -662,7 +757,8 @@ def disp_vec_vec_mul(func, typ): res += """ return res; end "{0}";\n""" - w(res.format(func,typ)) + w(res.format(func, typ)) + def disp_vec_int_mul(left, right): res = """ @@ -675,7 +771,8 @@ def disp_vec_int_mul(left, right): end if; return l * to_{0} (r, size); end "*";\n""" - w (res.format(left,right)) + w(res.format(left, right)) + def disp_int_vec_mul(left, right): res = """ @@ -688,27 +785,35 @@ def disp_int_vec_mul(left, right): end if; return r * to_{1} (l, size); end "*";\n""" - w (res.format(left,right)) + w(res.format(left, right)) + def disp_neg(func): - res = """ + res = ( + """ function "{func}" (ARG : SIGNED) return SIGNED is subtype arg_type is SIGNED (ARG'length - 1 downto 0); alias arga : arg_type is arg; variable res : arg_type; - variable carry, a : """ + logic_type() + """; + variable carry, a : """ + + logic_type() + + """; begin if arga'length = 0 then return null_signed; end if;""" - if logic == 'std': - res += """ - if has_0x (arga) = 'X' then""" + \ - disp_non_logical_warning("-") + """ + ) + if logic == "std": + res += ( + """ + if has_0x (arga) = 'X' then""" + + disp_non_logical_warning("-") + + """ return arg_type'(others => 'X'); end if;""" - if func == 'abs': + ) + if func == "abs": res += """ if arga (arga'left) = '0' then return arga; @@ -724,6 +829,7 @@ def disp_neg(func): end "{func}";\n""" w(res.format(func=func)) + def disp_has_0x(typ): res = """ function has_0x (a : {0}) return {1} @@ -731,8 +837,8 @@ def disp_has_0x(typ): variable res : {1} := '0'; begin for i in a'range loop""" - if logic == 'std': - res += """ + if logic == "std": + res += """ if a (i) = 'X' then return 'X'; end if;""" @@ -743,8 +849,10 @@ def disp_has_0x(typ): end has_0x;\n""" w(res.format(typ, logic_type())) + def disp_size(): - w(""" + w( + """ function size_unsigned (n : natural) return natural is -- At least one bit (even for 0). @@ -756,9 +864,11 @@ def disp_size(): n1 := n1 / 2; end loop; return res; - end size_unsigned;\n""") + end size_unsigned;\n""" + ) - w(""" + w( + """ function size_signed (n : integer) return natural is variable res : natural := 1; @@ -775,10 +885,13 @@ def disp_size(): n1 := n1 / 2; end loop; return res; - end size_signed;\n""") + end size_signed;\n""" + ) + def disp_divmod(): - w(""" + w( + """ -- All index range are normalized (N downto 0). -- NUM and QUOT have the same range. -- DEM and REMAIN have the same range. @@ -788,7 +901,9 @@ def disp_divmod(): -- An extra bit is needed so that it is always possible that DEM >= REG. variable reg : unsigned (dem'left + 1 downto 0) := (others => '0'); variable sub : unsigned (dem'range) := (others => '0'); - variable carry, d : """ + logic_type () + """; + variable carry, d : """ + + logic_type() + + """; begin for i in num'range loop -- Shift to add a new bit from NUM to REG. @@ -816,10 +931,13 @@ def disp_divmod(): end loop; remain := reg (dem'range); end divmod; -""") +""" + ) + def disp_vec_vec_udiv(func): - res = """ + res = ( + """ function "{func}" (L, R : UNSIGNED) return UNSIGNED is subtype l_type is UNSIGNED (L'length - 1 downto 0); @@ -828,32 +946,39 @@ def disp_vec_vec_udiv(func): alias ra : r_type is r; variable quot : l_type; variable rema : r_type; - variable r0 : """ + logic_type() + """ := has_0x (r); + variable r0 : """ + + logic_type() + + """ := has_0x (r); begin if la'length = 0 or ra'length = 0 then return null_unsigned; end if;""" - if logic == 'std': - res += """ - if has_0x (l) = 'X' or r0 = 'X' then""" + \ - disp_non_logical_warning ('/') + """ + ) + if logic == "std": + res += ( + """ + if has_0x (l) = 'X' or r0 = 'X' then""" + + disp_non_logical_warning("/") + + """ return l_type'(others => 'X'); end if;""" + ) res += """ assert r0 /= '0' report "NUMERIC_STD.""{func}"": division by 0" severity error; divmod (la, ra, quot, rema);""" - if func == '/': - res += """ + if func == "/": + res += """ return quot;""" else: - res += """ + res += """ return rema;""" res += """ end "{func}";\n""" w(res.format(func=func)) + def disp_vec_int_udiv(func): res = """ function "{func}" (L : UNSIGNED; R : NATURAL) return UNSIGNED @@ -863,7 +988,7 @@ def disp_vec_int_udiv(func): if l'length = 0 then return null_unsigned; end if;""" - if func in ['mod', 'rem']: + if func in ["mod", "rem"]: res += """ return resize (l {func} to_unsigned (r, r_size), l'length);""" else: @@ -881,7 +1006,7 @@ def disp_vec_int_udiv(func): if r'length = 0 then return null_unsigned; end if;""" - if func == '/': + if func == "/": res += """ return resize (to_unsigned (l, l_size) {func} r, r'length);""" else: @@ -891,8 +1016,10 @@ def disp_vec_int_udiv(func): end "{func}";\n""" w(res.format(func=func)) + def disp_vec_vec_sdiv(func): - res = """ + res = ( + """ function "{func}" (L, R : SIGNED) return SIGNED is subtype l_type is SIGNED (L'length - 1 downto 0); @@ -905,17 +1032,23 @@ def disp_vec_vec_sdiv(func): variable ru : r_utype; variable quot : l_utype; variable rema : r_utype; - variable r0 : """ + logic_type() + """ := has_0x (r); + variable r0 : """ + + logic_type() + + """ := has_0x (r); begin if la'length = 0 or ra'length = 0 then return null_signed; end if;""" - if logic == 'std': - res += """ - if has_0x (l) = 'X' or r0 = 'X' then""" + \ - disp_non_logical_warning (func) + """ + ) + if logic == "std": + res += ( + """ + if has_0x (l) = 'X' or r0 = 'X' then""" + + disp_non_logical_warning(func) + + """ return l_type'(others => 'X'); end if;""" + ) res += """ assert r0 /= '0' report "NUMERIC_STD.""{func}"": division by 0" @@ -932,14 +1065,14 @@ def disp_vec_vec_sdiv(func): ru := unsigned (ra); end if; divmod (lu, ru, quot, rema);""" - if func == '/': + if func == "/": res += """ if (ra (ra'left) xor la (la'left)) = '1' then return -signed (quot); else return signed (quot); end if;""" - elif func == 'rem': + elif func == "rem": res += """ -- Result of rem has the sign of the dividend. if la (la'left) = '1' then @@ -947,7 +1080,7 @@ def disp_vec_vec_sdiv(func): else return signed (rema); end if;""" - elif func == 'mod': + elif func == "mod": res += """ -- Result of mod has the sign of the divisor. if rema = r_utype'(others => '0') then @@ -972,6 +1105,7 @@ def disp_vec_vec_sdiv(func): end "{func}";\n""" w(res.format(func=func)) + def disp_vec_int_sdiv(func): res = """ function "{func}" (L : SIGNED; R : INTEGER) return SIGNED @@ -981,11 +1115,11 @@ def disp_vec_int_sdiv(func): if l'length = 0 then return null_signed; end if;""" - if func == '/': - res += """ + if func == "/": + res += """ return l {func} to_signed (r, r_size);""" else: - res += """ + res += """ return resize (l {func} to_signed (r, r_size), l'length);""" res += """ end "{func}";\n""" @@ -999,7 +1133,7 @@ def disp_vec_int_sdiv(func): if r'length = 0 then return null_signed; end if;""" - if func == '/': + if func == "/": res += """ return resize (to_signed (l, max (l_size, r'length)) {func} r, r'length);""" else: @@ -1009,8 +1143,9 @@ def disp_vec_int_sdiv(func): end "{func}";\n""" w(res.format(func=func)) + def disp_all_log_funcs(): - "Generate all function bodies for logic operators" + """Generate all function bodies for logic operators.""" for t in vec_types: disp_resize(t) for v in vec_types: @@ -1030,15 +1165,16 @@ def disp_all_log_funcs(): disp_vec_int_compare(f, "SIGNED", "INTEGER") disp_vec_int_compare(f, "INTEGER", "SIGNED") for t in vec_types: - for d in ['left', 'right']: - disp_shift('shift_' + d, t, d); - for d in ['left', 'right']: - disp_rotate('rotate_' + d, t, d); + for d in ["left", "right"]: + disp_shift("shift_" + d, t, d) + for d in ["left", "right"]: + disp_rotate("rotate_" + d, t, d) if v93: - disp_shift_op('"sll"', t, 'left') - disp_shift_op('"srl"', t, 'right') - disp_rotate('"rol"', t, 'left') - disp_rotate('"ror"', t, 'right') + disp_shift_op('"sll"', t, "left") + disp_shift_op('"srl"', t, "right") + disp_rotate('"rol"', t, "left") + disp_rotate('"ror"', t, "right") + def disp_match(typ): res = """ @@ -1070,75 +1206,83 @@ def disp_match(typ): def disp_all_match_funcs(): - disp_match('std_ulogic_vector'); - disp_match('std_logic_vector'); - disp_match('UNSIGNED'); - disp_match('SIGNED'); + disp_match("std_ulogic_vector") + disp_match("std_logic_vector") + disp_match("UNSIGNED") + disp_match("SIGNED") + def disp_all_arith_funcs(): - "Generate all function bodies for logic operators" - for op in ['+', '-']: + """Generate all function bodies for logic operators.""" + for op in ["+", "-"]: disp_vec_vec_binary(op, "UNSIGNED") disp_vec_vec_binary(op, "SIGNED") disp_vec_int_binary(op, "UNSIGNED", "NATURAL") disp_vec_int_binary(op, "NATURAL", "UNSIGNED") disp_vec_int_binary(op, "SIGNED", "INTEGER") disp_vec_int_binary(op, "INTEGER", "SIGNED") - disp_vec_vec_mul('*', 'UNSIGNED') - disp_vec_vec_mul('*', 'SIGNED') - disp_vec_int_mul('UNSIGNED', 'NATURAL') - disp_vec_int_mul('SIGNED', 'INTEGER') - disp_int_vec_mul('NATURAL', 'UNSIGNED') - disp_int_vec_mul('INTEGER', 'SIGNED') - disp_has_0x('UNSIGNED') + disp_vec_vec_mul("*", "UNSIGNED") + disp_vec_vec_mul("*", "SIGNED") + disp_vec_int_mul("UNSIGNED", "NATURAL") + disp_vec_int_mul("SIGNED", "INTEGER") + disp_int_vec_mul("NATURAL", "UNSIGNED") + disp_int_vec_mul("INTEGER", "SIGNED") + disp_has_0x("UNSIGNED") disp_divmod() disp_size() - disp_vec_vec_udiv('/') - disp_vec_int_udiv('/') - disp_vec_vec_udiv('rem') - disp_vec_int_udiv('rem') - disp_vec_vec_udiv('mod') - disp_vec_int_udiv('mod') - disp_has_0x('SIGNED') + disp_vec_vec_udiv("/") + disp_vec_int_udiv("/") + disp_vec_vec_udiv("rem") + disp_vec_int_udiv("rem") + disp_vec_vec_udiv("mod") + disp_vec_int_udiv("mod") + disp_has_0x("SIGNED") disp_neg("-") disp_neg("abs") - disp_vec_vec_sdiv('/') - disp_vec_int_sdiv('/') - disp_vec_vec_sdiv('rem') - disp_vec_int_sdiv('rem') - disp_vec_vec_sdiv('mod') - disp_vec_int_sdiv('mod') + disp_vec_vec_sdiv("/") + disp_vec_int_sdiv("/") + disp_vec_vec_sdiv("rem") + disp_vec_int_sdiv("rem") + disp_vec_vec_sdiv("mod") + disp_vec_int_sdiv("mod") + # Patterns to replace -pats = {' @LOG\n' : disp_all_log_funcs, - ' @ARITH\n' : disp_all_arith_funcs, - ' @MATCH\n' : disp_all_match_funcs } +pats = { + " @LOG\n": disp_all_log_funcs, + " @ARITH\n": disp_all_arith_funcs, + " @MATCH\n": disp_all_match_funcs, +} + +spec_file = "numeric_std.vhdl" +# proto_file='numeric_std-body.proto' -spec_file='numeric_std.vhdl' -#proto_file='numeric_std-body.proto' def gen_body(proto_file): - w('-- This -*- vhdl -*- file was generated from ' + proto_file + '\n') + w("-- This -*- vhdl -*- file was generated from " + proto_file + "\n") for line in open(proto_file): if line in pats: pats[line]() continue w(line) + # Copy spec for log in logics: - for std in ['87', '93']: - out=open('v' + std + '/numeric_' + log + '.vhdl', 'w') - for line in open('numeric_' + log + '.proto'): - if line == ' @COMMON\n': - for lcom in open('numeric_common.proto'): - if lcom[0:2] == '--': + for std in ["87", "93"]: + out = open("v" + std + "/numeric_" + log + ".vhdl", "w") + for line in open("numeric_" + log + ".proto"): + if line == " @COMMON\n": + for lcom in open("numeric_common.proto"): + if lcom[0:2] == "--": pass - elif std == '87' and ('"xnor"' in lcom - or '"sll"' in lcom - or '"srl"' in lcom - or '"rol"' in lcom - or '"ror"' in lcom): + elif std == "87" and ( + '"xnor"' in lcom + or '"sll"' in lcom + or '"srl"' in lcom + or '"rol"' in lcom + or '"ror"' in lcom + ): w("--" + lcom[2:]) else: w(lcom) @@ -1147,17 +1291,17 @@ for log in logics: out.close() # Generate bodies -v93=False +v93 = False for l in logics: logic = l - out=open('v87/numeric_{0}-body.vhdl'.format(l), 'w') - gen_body('numeric_{0}-body.proto'.format(l)) + out = open("v87/numeric_{0}-body.vhdl".format(l), "w") + gen_body("numeric_{0}-body.proto".format(l)) out.close() -v93=True +v93 = True binary_funcs.append("xnor") for l in logics: logic = l - out=open('v93/numeric_{0}-body.vhdl'.format(l), 'w') - gen_body('numeric_{0}-body.proto'.format(l)) + out = open("v93/numeric_{0}-body.vhdl".format(l), "w") + gen_body("numeric_{0}-body.proto".format(l)) out.close() |