4 files changed, 46 insertions, 12 deletions

diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index 53cc03395..ce93bda3e 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -42,13 +42,16 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 from pyGHDL.libghdl._types import Iir
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (Entity as VHDLModel_Entity, EntityOrSymbol,
- Architecture as VHDLModel_Architecture,
- Package as VHDLModel_Package,
- PackageBody as VHDLModel_PackageBody,
- Context as VHDLModel_Context,
-Configuration as VHDLModel_Configuration,
-Component as VHDLModel_Component)
+from pyVHDLModel.VHDLModel import (
+    Entity as VHDLModel_Entity,
+    EntityOrSymbol,
+    Architecture as VHDLModel_Architecture,
+    Package as VHDLModel_Package,
+    PackageBody as VHDLModel_PackageBody,
+    Context as VHDLModel_Context,
+    Configuration as VHDLModel_Configuration,
+    Component as VHDLModel_Component,
+)
 
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom._Utils import GetNameOfNode
@@ -71,9 +74,7 @@ class Entity(VHDLModel_Entity, GHDLMixin):
         name = GetNameOfNode(entityNode)
         entity = cls(name)
 
-        for generic in GetGenericsFromChainedNodes(
-            nodes.Get_Generic_Chain(entityNode)
-        ):
+        for generic in GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(entityNode)):
             entity.GenericItems.append(generic)
 
         for port in GetPortsFromChainedNodes(nodes.Get_Port_Chain(entityNode)):
diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index 78f3f279a..4fe3a843c 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -39,6 +39,8 @@ from pydecor import export
 from pyVHDLModel.VHDLModel import (
     IntegerLiteral as VHDLModel_IntegerLiteral,
     FloatingPointLiteral as VHDLModel_FloatingPointLiteral,
+    PhysicalIntegerLiteral as VHDLModel_PhysicalIntegerLiteral,
+    PhysicalFloatingLiteral as VHDLModel_PhysicalFloatingLiteral,
     CharacterLiteral as VHDLModel_CharacterLiteral,
     StringLiteral as VHDLModel_StringLiteral,
 )
@@ -63,6 +65,28 @@ class FloatingPointLiteral(VHDLModel_FloatingPointLiteral):
 
 
 @export
+class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral):
+    @classmethod
+    def parse(cls, node):
+        value = nodes.Get_Value(node)
+        unit = nodes.Get_Unit_Name(node)
+        unitName = name_table.Get_Name_Ptr(unit)
+
+        return cls(value, unitName)
+
+
+@export
+class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral):
+    @classmethod
+    def parse(cls, node):
+        value = nodes.Get_Fp_Value(node)
+        unit = nodes.Get_Unit_Name(node)
+        unitName = name_table.Get_Name_Ptr(unit)
+
+        return cls(value, unitName)
+
+
+@export
 class CharacterLiteral(VHDLModel_CharacterLiteral):
     @classmethod
     def parse(cls, node):
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index e29a9f827..7d736f335 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -61,6 +61,8 @@ from pyGHDL.dom.Literal import (
     CharacterLiteral,
     FloatingPointLiteral,
     StringLiteral,
+    PhysicalIntegerLiteral,
+    PhysicalFloatingLiteral,
 )
 from pyGHDL.dom.Expression import (
     SubtractionExpression,
@@ -194,6 +196,8 @@ __EXPRESSION_TRANSLATION = {
     nodes.Iir_Kind.Parenthesis_Name: IndexedObjectOrFunctionCallSymbol,
     nodes.Iir_Kind.Integer_Literal: IntegerLiteral,
     nodes.Iir_Kind.Floating_Point_Literal: FloatingPointLiteral,
+    nodes.Iir_Kind.Physical_Int_Literal: PhysicalIntegerLiteral,
+    nodes.Iir_Kind.Physical_Fp_Literal: PhysicalFloatingLiteral,
     nodes.Iir_Kind.Character_Literal: CharacterLiteral,
     nodes.Iir_Kind.String_Literal8: StringLiteral,
     nodes.Iir_Kind.Negation_Operator: NegationExpression,
@@ -302,6 +306,8 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str):
             from pyGHDL.dom.Object import Signal
 
             result.append(Signal.parse(item))
+        elif kind == nodes.Iir_Kind.Type_Declaration:
+            result.append(GetTypeFromNode(item))
         elif kind == nodes.Iir_Kind.Anonymous_Type_Declaration:
             result.append(GetTypeFromNode(item))
         elif kind == nodes.Iir_Kind.Subtype_Declaration:
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index 7d07abcfe..cdb1964c0 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -20,7 +20,8 @@ from pyGHDL.dom.DesignUnit import (
     Package,
     PackageBody,
     Configuration,
-    Context, Component,
+    Context,
+    Component,
 )
 from pyGHDL.dom.Object import Constant, Signal
 from pyGHDL.dom.InterfaceItem import (
@@ -167,7 +168,9 @@ class PrettyPrint:
     def formatComponent(self, component: Component, level: int = 0) -> StringBuffer:
         buffer = []
         prefix = "  " * level
-        buffer.append("{prefix}- Component: {name}".format(name=component.Name, prefix=prefix))
+        buffer.append(
+            "{prefix}- Component: {name}".format(name=component.Name, prefix=prefix)
+        )
         buffer.append("{prefix}  Generics:".format(prefix=prefix))
         for generic in component.GenericItems:
             for line in self.formatGeneric(generic, level + 1):