diff options
Diffstat (limited to 'pyGHDL')
| -rw-r--r-- | pyGHDL/dom/Expression.py | 40 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 50 |
2 files changed, 71 insertions, 19 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index d55ea8cef..30684394b 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -39,7 +39,7 @@ from pyVHDLModel.VHDLModel import ( IdentityExpression as VHDLModel_IdentityExpression, NegationExpression as VHDLModel_NegationExpression, AbsoluteExpression as VHDLModel_AbsoluteExpression, - ParenthesisExpression as VHDLModel_ParenthesisExpression, + SubExpression as VHDLModel_ParenthesisExpression, TypeConversion as VHDLModel_TypeConversion, FunctionCall as VHDLModel_FunctionCall, QualifiedExpression as VHDLModel_QualifiedExpression, @@ -59,9 +59,10 @@ from pyVHDLModel.VHDLModel import ( XnorExpression as VHDLModel_XnorExpression, EqualExpression as VHDLModel_EqualExpression, UnequalExpression as VHDLModel_UnequalExpression, + LessThanExpression as VHDLModel_LessThanExpression, + LessEqualExpression as VHDLModel_LessEqualExpression, GreaterThanExpression as VHDLModel_GreaterThanExpression, GreaterEqualExpression as VHDLModel_GreaterEqualExpression, - LessThanExpression as VHDLModel_LessThanExpression, ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, @@ -70,14 +71,14 @@ from pyVHDLModel.VHDLModel import ( RotateLeftExpression as VHDLModel_RotateLeftExpression, Aggregate as VHDLModel_Aggregate, Expression, - AggregateElement, + AggregateElement, SubTypeOrSymbol, ) from pyGHDL.libghdl import utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom.Common import DOMException -from pyGHDL.dom.Symbol import EnumerationLiteralSymbol +from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol from pyGHDL.dom.Aggregates import ( OthersAggregateElement, SimpleAggregateElement, @@ -305,7 +306,7 @@ class UnequalExpression(VHDLModel_UnequalExpression, _ParseBinaryExpression): @export -class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression): +class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -313,7 +314,7 @@ class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpress @export -class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression): +class LessEqualExpression(VHDLModel_LessEqualExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -321,7 +322,15 @@ class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpre @export -class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression): +class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression): + def __init__(self, left: Expression, right: Expression): + super().__init__() + self._leftOperand = left + self._rightOperand = right + + +@export +class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -385,6 +394,23 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, _ParseBinaryExpressio @export +class QualifiedExpression(VHDLModel_QualifiedExpression): + def __init__(self, subType: SubTypeOrSymbol, operand: Expression): + super().__init__() + self._subtype = subType + self._operand = operand + + @classmethod + def parse(cls, node): + from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode + + typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) + subType = SimpleSubTypeSymbol(typeMarkName) + operand = GetExpressionFromNode(nodes.Get_Expression(node)) + return cls(subType, operand) + + +@export class Aggregate(VHDLModel_Aggregate): def __init__(self, elements: List[AggregateElement]): super().__init__() diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index a18f738df..2445d0574 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -56,7 +56,10 @@ from pyGHDL.dom.Expression import ( ExponentiationExpression, Aggregate, NegationExpression, - ParenthesisExpression, ConcatenationExpression, + ParenthesisExpression, ConcatenationExpression, QualifiedExpression, ModuloExpression, RemainderExpression, AndExpression, NandExpression, OrExpression, + NorExpression, XorExpression, XnorExpression, EqualExpression, UnequalExpression, LessThanExpression, GreaterThanExpression, GreaterEqualExpression, + LessEqualExpression, ShiftLeftLogicExpression, ShiftRightLogicExpression, ShiftLeftArithmeticExpression, ShiftRightArithmeticExpression, + RotateLeftExpression, RotateRightExpression, ) __all__ = [] @@ -118,6 +121,19 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai return constraints +@export +def GetRangeFromNode(node) -> Range: + direction = nodes.Get_Direction(node) + leftBound = nodes.Get_Left_Limit_Expr(node) + rightBound = nodes.Get_Right_Limit_Expr(node) + + return Range( + GetExpressionFromNode(leftBound), + GetExpressionFromNode(rightBound), + Direction.DownTo if direction else Direction.To, + ) + + __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Simple_Name: SimpleObjectSymbol, nodes.Iir_Kind.Integer_Literal: IntegerLiteral, @@ -132,21 +148,31 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Substraction_Operator: SubtractionExpression, nodes.Iir_Kind.Multiplication_Operator: MultiplyExpression, nodes.Iir_Kind.Division_Operator: DivisionExpression, + nodes.Iir_Kind.Modulus_Operator: ModuloExpression, + nodes.Iir_Kind.Remainder_Operator: RemainderExpression, nodes.Iir_Kind.Exponentiation_Operator: ExponentiationExpression, + nodes.Iir_Kind.And_Operator: AndExpression, + nodes.Iir_Kind.Nand_Operator: NandExpression, + nodes.Iir_Kind.Or_Operator: OrExpression, + nodes.Iir_Kind.Nor_Operator: NorExpression, + nodes.Iir_Kind.Xor_Operator: XorExpression, + nodes.Iir_Kind.Xnor_Operator: XnorExpression, + nodes.Iir_Kind.Equality_Operator: EqualExpression, + nodes.Iir_Kind.Inequality_Operator: UnequalExpression, + nodes.Iir_Kind.Less_Than_Operator: LessThanExpression, + nodes.Iir_Kind.Less_Than_Or_Equal_Operator: LessEqualExpression, + nodes.Iir_Kind.Greater_Than_Operator: GreaterThanExpression, + nodes.Iir_Kind.Greater_Than_Or_Equal_Operator: GreaterEqualExpression, + nodes.Iir_Kind.Sll_Operator: ShiftLeftLogicExpression, + nodes.Iir_Kind.Srl_Operator: ShiftRightLogicExpression, + nodes.Iir_Kind.Sla_Operator: ShiftLeftArithmeticExpression, + nodes.Iir_Kind.Sra_Operator: ShiftRightArithmeticExpression, + nodes.Iir_Kind.Rol_Operator: RotateLeftExpression, + nodes.Iir_Kind.Ror_Operator: RotateRightExpression, + nodes.Iir_Kind.Qualified_Expression: QualifiedExpression, nodes.Iir_Kind.Aggregate: Aggregate, } -@export -def GetRangeFromNode(node) -> Range: - direction = nodes.Get_Direction(node) - leftBound = nodes.Get_Left_Limit_Expr(node) - rightBound = nodes.Get_Right_Limit_Expr(node) - - return Range( - GetExpressionFromNode(leftBound), - GetExpressionFromNode(rightBound), - Direction.DownTo if direction else Direction.To, - ) @export def GetExpressionFromNode(node) -> Expression: |