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-rw-r--r--src/simul/simul-vhdl_elab.adb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index f3ca2ff87..884d83c28 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -102,7 +102,8 @@ package body Simul.Vhdl_Elab is
Across_Typ := Get_Subtype_Object (Inst, Get_Across_Type (Def));
Through_Typ := Get_Subtype_Object (Inst, Get_Through_Type (Def));
pragma Assert (Val.Val.T = No_Terminal_Index);
- Terminal_Table.Append ((Decl, Inst, Across_Typ, Through_Typ, null));
+ Terminal_Table.Append ((Decl, Inst, Across_Typ, Through_Typ, null,
+ No_Scalar_Quantity, No_Scalar_Terminal));
Val.Val.T := Terminal_Table.Last;
end Gather_Terminal;