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-rw-r--r--src/simul/simul-vhdl_simul.ads4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads
index 38d3173f0..f2cf98212 100644
--- a/src/simul/simul-vhdl_simul.ads
+++ b/src/simul/simul-vhdl_simul.ads
@@ -18,7 +18,7 @@
with Types; use Types;
with Tables;
-with Areapools; use Areapools;
+with Areapools;
with Vhdl.Nodes; use Vhdl.Nodes;
@@ -60,7 +60,7 @@ package Simul.Vhdl_Simul is
case Kind is
when Kind_Process =>
-- Memory pool to allocate objects from.
- Pool : Areapool_Acc;
+ Pool : Areapools.Areapool_Acc;
when Kind_PSL =>
Done : Boolean;
States: Boolean_Vector_Acc;