diff options
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index 70badeb34..a5566b0c7 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -482,10 +482,16 @@ package Std_Names is Name_VITAL_Timing : constant Name_Id := Name_First_Ieee + 008; Name_VITAL_Level0 : constant Name_Id := Name_First_Ieee + 009; Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; - Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 011; - Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 012; - Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 013; - Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 014; + Name_Numeric_Std : constant Name_Id := Name_First_Ieee + 011; + Name_Numeric_Bit : constant Name_Id := Name_First_Ieee + 012; + Name_Unsigned : constant Name_Id := Name_First_Ieee + 013; + Name_Signed : constant Name_Id := Name_First_Ieee + 014; + Name_Unresolved_Unsigned : constant Name_Id := Name_First_Ieee + 015; + Name_Unresolved_Signed : constant Name_Id := Name_First_Ieee + 016; + Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 017; + Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 018; + Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 019; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 020; Name_Last_Ieee : constant Name_Id := Name_Std_Logic_Unsigned; -- Verilog keywords. |