1 files changed, 45 insertions, 22 deletions

diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb
index 848adc05b..cd13a6d77 100644
--- a/src/synth/netlists-disp_verilog.adb
+++ b/src/synth/netlists-disp_verilog.adb
@@ -31,6 +31,10 @@ package body Netlists.Disp_Verilog is
    Flag_Merge_Lit : constant Boolean := True;
    Flag_Merge_Edge : constant Boolean := True;
 
+   --  Wires/regs/parameters of size 0 are not possible in verilog.
+   --  Do not display them.
+   Flag_Null_Wires : constant Boolean := False;
+
    procedure Put_Type (W : Width) is
    begin
       if W > 1 then
@@ -158,10 +162,12 @@ package body Netlists.Disp_Verilog is
    is
       Imod : constant Module := Get_Module (Inst);
       Idx : Port_Idx;
+      Drv : Net;
       Max_Idx : Port_Idx;
       Name : Sname;
       First : Boolean;
       Param : Param_Desc;
+      Desc : Port_Desc;
    begin
       Put ("  ");
 
@@ -217,33 +223,37 @@ package body Netlists.Disp_Verilog is
       Idx := 0;
       Max_Idx := Get_Nbr_Inputs (Imod);
       for I of Inputs (Inst) loop
-         if First then
-            First := False;
-         else
-            Put_Line (",");
-         end if;
-         Put ("    ");
-         if Idx < Max_Idx then
-            Put (".");
-            Put_Interface_Name (Get_Input_Desc (Imod, Idx).Name);
-            Put ("(");
-         end if;
-         Disp_Net_Name (Get_Driver (I));
-         if Idx < Max_Idx then
-            Put (")");
-            Idx := Idx + 1;
+         Drv := Get_Driver (I);
+         if Flag_Null_Wires or else Get_Width (Drv) /= 0 then
+            if First then
+               First := False;
+            else
+               Put_Line (",");
+            end if;
+            Put ("    ");
+            if Idx < Max_Idx then
+               Put (".");
+               Put_Interface_Name (Get_Input_Desc (Imod, Idx).Name);
+               Put ("(");
+            end if;
+            Disp_Net_Name (Get_Driver (I));
+            if Idx < Max_Idx then
+               Put (")");
+            end if;
          end if;
+         Idx := Idx + 1;
       end loop;
       --  Outputs
       Idx := 0;
       for O of Outputs (Inst) loop
+         Desc := Get_Output_Desc (Imod, Idx);
          if First then
             First := False;
          else
             Put_Line (",");
          end if;
          Put ("    .");
-         Put_Interface_Name (Get_Output_Desc (Imod, Idx).Name);
+         Put_Interface_Name (Desc.Name);
          Idx := Idx + 1;
          Put ("(");
          declare
@@ -434,9 +444,14 @@ package body Netlists.Disp_Verilog is
    --  a name.  In that case, a signal will be created and driven.
    function Need_Signal (Inst : Instance) return Boolean
    is
+      O : constant Net := Get_Output (Inst, 0);
       I : Input;
    begin
-      I := Get_First_Sink (Get_Output (Inst, 0));
+      if not Flag_Null_Wires and then Get_Width (O) = 0 then
+         return False;
+      end if;
+
+      I := Get_First_Sink (O);
       while I /= No_Input loop
          if Need_Name (Get_Input_Parent (I)) then
             return True;
@@ -1212,14 +1227,18 @@ package body Netlists.Disp_Verilog is
       --  Output assignments.
       declare
          Idx : Port_Idx;
+         Desc : Port_Desc;
       begin
          Idx := 0;
          for I of Inputs (Self_Inst) loop
-            Put ("  assign ");
-            Put_Name (Get_Output_Desc (M, Idx).Name);
-            Put (" = ");
-            Disp_Net_Name (Get_Driver (I));
-            Put_Line (";");
+            Desc := Get_Output_Desc (M, Idx);
+            if Desc.W /= 0 or Flag_Null_Wires then
+               Put ("  assign ");
+               Put_Name (Desc.Name);
+               Put (" = ");
+               Disp_Net_Name (Get_Driver (I));
+               Put_Line (";");
+            end if;
             Idx := Idx + 1;
          end loop;
       end;
@@ -1246,6 +1265,10 @@ package body Netlists.Disp_Verilog is
    is
       Attr : Attribute;
    begin
+      if not (Desc.W /= 0 or Flag_Null_Wires) then
+         return;
+      end if;
+
       if First then
          Put ("  (");
          First := False;