diff options
Diffstat (limited to 'src/synth/synth-vhdl_decls.adb')
| -rw-r--r-- | src/synth/synth-vhdl_decls.adb | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index 19473775f..f1e42c97b 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -659,12 +659,12 @@ package body Synth.Vhdl_Decls is if Aval.Val.Kind = Value_Net then -- Object is a net if it is not writable. Extract the -- bits for the alias. - Current_Pool := Instance_Pool; - Aval := Create_Value_Net - (Build2_Extract (Get_Build (Syn_Inst), Get_Value_Net (Aval.Val), - Off, Val.Typ.W), - Val.Typ); - Current_Pool := Expr_Pool'Access; + Aval := (Val.Typ, + Create_Value_Net (Build2_Extract + (Get_Build (Syn_Inst), + Get_Value_Net (Aval.Val), + Off, Val.Typ.W), + Instance_Pool)); Val.Val.A_Off := (0, 0); else Aval := Unshare (Aval, Instance_Pool); @@ -844,6 +844,14 @@ package body Synth.Vhdl_Decls is Finalize_Assignment (Get_Build (Syn_Inst), W); Gate_Net := Get_Wire_Gate (W); + + Free_Wire (W); + + -- Replace the wire with a net so that external names can refer to it. + Mutate_Object + (Syn_Inst, Decl, + (Vt.Typ, Create_Value_Net (Gate_Net, Process_Pool'Access))); + Gate := Get_Net_Parent (Gate_Net); case Get_Id (Gate) is when Id_Signal @@ -883,8 +891,6 @@ package body Synth.Vhdl_Decls is -- The value of an undriven signal is its initial value. Connect (Get_Input (Gate, 0), Def_Val); end if; - - Free_Wire (W); end Finalize_Signal; procedure Finalize_Declaration |