diff options
Diffstat (limited to 'src/synth/synth-vhdl_insts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_insts.adb | 89 |
1 files changed, 69 insertions, 20 deletions
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index 458981f37..2d3f3360f 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -186,11 +186,25 @@ package body Synth.Vhdl_Insts is begin case Typ.Kind is when Type_Vector => - Hash_Bound (C, Typ.Vbound); + Hash_Bound (C, Typ.Abound); when Type_Array => - for I in Typ.Abounds.D'Range loop - Hash_Bound (C, Typ.Abounds.D (I)); + declare + T : Type_Acc; + begin + T := Typ; + loop + Hash_Bound (C, T.Abound); + exit when T.Alast; + T := T.Arr_El; + end loop; + end; + when Type_Record => + for I in Typ.Rec.E'Range loop + Hash_Bounds (C, Typ.Rec.E (I).Typ); end loop; + when Type_Bit + | Type_Logic => + null; when others => raise Internal_Error; end case; @@ -213,7 +227,8 @@ package body Synth.Vhdl_Insts is when Value_Net | Value_Wire | Value_Signal - | Value_File => + | Value_File + | Value_Dyn_Alias => raise Internal_Error; end case; end Hash_Const; @@ -623,6 +638,40 @@ package body Synth.Vhdl_Insts is end if; end Interning_Get; + function Synth_Single_Input_Assoc (Syn_Inst : Synth_Instance_Acc; + Inter_Typ : Type_Acc; + Act_Inst : Synth_Instance_Acc; + Actual : Node; + Assoc : Node) return Valtyp + is + Ctxt : constant Context_Acc := Get_Build (Syn_Inst); + Conv : Node; + Act : Valtyp; + begin + if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Name then + Conv := Get_Actual_Conversion (Assoc); + else + Conv := Null_Node; + end if; + if Conv /= Null_Node then + case Get_Kind (Conv) is + when Iir_Kind_Function_Call => + pragma Assert (Act_Inst = Syn_Inst); + -- This is an abuse, but it works like a user operator. + Act := Synth_User_Operator (Syn_Inst, Actual, Null_Node, Conv); + when Iir_Kind_Type_Conversion => + Act := Synth_Type_Conversion (Syn_Inst, Conv); + when others => + Vhdl.Errors.Error_Kind ("synth_single_input_assoc", Conv); + end case; + else + Act := Synth_Expression_With_Type (Act_Inst, Actual, Inter_Typ); + end if; + + Act := Synth_Subtype_Conversion (Ctxt, Act, Inter_Typ, False, Assoc); + return Act; + end Synth_Single_Input_Assoc; + procedure Synth_Individual_Prefix (Syn_Inst : Synth_Instance_Acc; Inter_Inst : Synth_Instance_Acc; Formal : Node; @@ -643,23 +692,25 @@ package body Synth.Vhdl_Insts is begin Synth_Individual_Prefix (Syn_Inst, Inter_Inst, Get_Prefix (Formal), Off, Typ); - Off := Off + Typ.Rec.E (Idx + 1).Boff; + Off := Off + Typ.Rec.E (Idx + 1).Offs.Net_Off; Typ := Typ.Rec.E (Idx + 1).Typ; end; when Iir_Kind_Indexed_Name => declare + El_Typ : Type_Acc; Voff : Net; Arr_Off : Value_Offsets; Err : Boolean; begin Synth_Individual_Prefix (Syn_Inst, Inter_Inst, Get_Prefix (Formal), Off, Typ); - Synth_Indexed_Name (Syn_Inst, Formal, Typ, Voff, Arr_Off, Err); + Synth_Indexed_Name (Syn_Inst, Formal, Typ, + El_Typ, Voff, Arr_Off, Err); if Voff /= No_Net or Err then raise Internal_Error; end if; Off := Off + Arr_Off.Net_Off; - Typ := Get_Array_Element (Typ); + Typ := El_Typ; end; when Iir_Kind_Slice_Name => declare @@ -745,7 +796,8 @@ package body Synth.Vhdl_Insts is (Syn_Inst, Inter_Inst, Get_Formal (Iassoc), Off, Typ); -- 2. synth expression - V := Synth_Expression_With_Type (Syn_Inst, Get_Actual (Iassoc), Typ); + V := Synth_Single_Input_Assoc + (Syn_Inst, Typ, Syn_Inst, Get_Actual (Iassoc), Iassoc); -- 3. save in a table Value_Offset_Tables.Append (Els, (Off, V)); @@ -781,28 +833,25 @@ package body Synth.Vhdl_Insts is return Net is Ctxt : constant Context_Acc := Get_Build (Syn_Inst); - Actual : Node; - Act_Inst : Synth_Instance_Acc; - Act : Valtyp; + Res : Valtyp; begin case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is when Iir_Kind_Association_Element_Open => - Actual := Get_Default_Value (Inter); - Act_Inst := Inter_Inst; + Res := Synth_Single_Input_Assoc + (Syn_Inst, Inter_Typ, Inter_Inst, + Get_Default_Value (Inter), Assoc); when Iir_Kind_Association_Element_By_Expression | Iir_Kind_Association_Element_By_Name => - Actual := Get_Actual (Assoc); - Act_Inst := Syn_Inst; + Res := Synth_Single_Input_Assoc + (Syn_Inst, Inter_Typ, Syn_Inst, Get_Actual (Assoc), Assoc); when Iir_Kind_Association_Element_By_Individual => return Synth_Individual_Input_Assoc (Syn_Inst, Assoc, Inter_Inst); end case; - Act := Synth_Expression_With_Type (Act_Inst, Actual, Inter_Typ); - Act := Synth_Subtype_Conversion (Ctxt, Act, Inter_Typ, False, Assoc); - if Act = No_Valtyp then + if Res = No_Valtyp then return No_Net; end if; - return Get_Net (Ctxt, Act); + return Get_Net (Ctxt, Res); end Synth_Input_Assoc; procedure Synth_Individual_Output_Assoc (Outp : Net; @@ -898,7 +947,7 @@ package body Synth.Vhdl_Insts is if N /= No_Net then Connect (Get_Input (Inst, Port), Build_Extract (Get_Build (Syn_Inst), N, - Inter_Typ.Rec.E (I).Boff, + Inter_Typ.Rec.E (I).Offs.Net_Off, Inter_Typ.Rec.E (I).Typ.W)); end if; Port := Port + 1; |