diff options
Diffstat (limited to 'src/synth/synth-vhdl_oper.adb')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 131 |
1 files changed, 80 insertions, 51 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 640a65b77..919d1f64e 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -143,13 +143,13 @@ package body Synth.Vhdl_Oper is case Res.Kind is when Type_Vector => - if Res.Vbound.Dir = Dir_Downto - and then Res.Vbound.Right = 0 + if Res.Abound.Dir = Dir_Downto + and then Res.Abound.Right = 0 then -- Normalized range return Res; end if; - return Create_Vec_Type_By_Length (Res.W, Res.Vec_El); + return Create_Vec_Type_By_Length (Res.W, Res.Arr_El); when Type_Slice => return Create_Vec_Type_By_Length (Res.W, Res.Slice_El); @@ -263,9 +263,9 @@ package body Synth.Vhdl_Oper is begin -- Note: LEFT or RIGHT can be a single bit. if Left.Typ.Kind = Type_Vector then - El_Typ := Left.Typ.Vec_El; + El_Typ := Left.Typ.Arr_El; elsif Right.Typ.Kind = Type_Vector then - El_Typ := Right.Typ.Vec_El; + El_Typ := Right.Typ.Arr_El; else raise Internal_Error; end if; @@ -461,20 +461,6 @@ package body Synth.Vhdl_Oper is return Create_Value_Net (N, Res_Type); end Synth_Compare; - function Synth_Minmax (Id : Compare_Module_Id) return Valtyp - is - L : constant Net := Get_Net (Ctxt, Left); - R : constant Net := Get_Net (Ctxt, Right); - Sel, N : Net; - begin - pragma Assert (Left_Type = Right_Type); - Sel := Build2_Compare (Ctxt, Id, L, R); - Set_Location (Sel, Expr); - N := Build_Mux2 (Ctxt, Sel, R, L); - Set_Location (N, Expr); - return Create_Value_Net (N, Expr_Typ); - end Synth_Minmax; - function Synth_Compare_Array (Id : Compare_Module_Id; Res_Type : Type_Acc) return Valtyp is @@ -635,7 +621,7 @@ package body Synth.Vhdl_Oper is when Oper_Right => Res_Typ := Right.Typ; end case; - Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Vec_El); + Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Arr_El); N := Build_Dyadic (Ctxt, Id, L1, R1); Set_Location (N, Expr); N := Build2_Uresize (Ctxt, N, Res_Typ.W, Get_Location (Expr)); @@ -658,7 +644,7 @@ package body Synth.Vhdl_Oper is when Oper_Right => Res_Typ := Right.Typ; end case; - Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Vec_El); + Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Arr_El); N := Build_Dyadic (Ctxt, Id, L1, R1); Set_Location (N, Expr); N := Build2_Sresize (Ctxt, N, Res_Typ.W, Get_Location (Expr)); @@ -788,28 +774,33 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_1164_Scalar_Xnor => return Synth_Bit_Dyadic (Id_Xnor); - when Iir_Predefined_Ieee_1164_Vector_And + when Iir_Predefined_TF_Array_And + | Iir_Predefined_Ieee_1164_Vector_And | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn => return Synth_Vec_Dyadic (Id_And); - when Iir_Predefined_Ieee_1164_Vector_Or + when Iir_Predefined_TF_Array_Or + | Iir_Predefined_Ieee_1164_Vector_Or | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Or); - when Iir_Predefined_Ieee_1164_Vector_Nand + when Iir_Predefined_TF_Array_Nand + | Iir_Predefined_Ieee_1164_Vector_Nand | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Nand); - when Iir_Predefined_Ieee_1164_Vector_Nor + when Iir_Predefined_TF_Array_Nor + | Iir_Predefined_Ieee_1164_Vector_Nor | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Nor); when Iir_Predefined_TF_Array_Xor - | Iir_Predefined_Ieee_1164_Vector_Xor - | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns - | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn => + | Iir_Predefined_Ieee_1164_Vector_Xor + | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Xor); - when Iir_Predefined_Ieee_1164_Vector_Xnor + when Iir_Predefined_TF_Array_Xnor + | Iir_Predefined_Ieee_1164_Vector_Xnor | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Xnor); @@ -974,7 +965,7 @@ package body Synth.Vhdl_Oper is Bnd := Create_Bounds_From_Length (Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), - Iir_Index32 (Get_Bound_Length (Left.Typ, 1) + 1)); + Iir_Index32 (Get_Bound_Length (Left.Typ) + 1)); Res_Typ := Create_Onedimensional_Array_Subtype (Left_Typ, Bnd, Le_Typ); @@ -994,7 +985,7 @@ package body Synth.Vhdl_Oper is Bnd := Create_Bounds_From_Length (Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), - Iir_Index32 (Get_Bound_Length (Right.Typ, 1) + 1)); + Iir_Index32 (Get_Bound_Length (Right.Typ) + 1)); Res_Typ := Create_Onedimensional_Array_Subtype (Right_Typ, Bnd, Re_Typ); @@ -1032,8 +1023,8 @@ package body Synth.Vhdl_Oper is Bnd := Create_Bounds_From_Length (Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), - Iir_Index32 (Get_Bound_Length (Left.Typ, 1) - + Get_Bound_Length (Right.Typ, 1))); + Iir_Index32 (Get_Bound_Length (Left.Typ) + + Get_Bound_Length (Right.Typ))); Res_Typ := Create_Onedimensional_Array_Subtype (Expr_Typ, Bnd, Le_Typ); @@ -1088,10 +1079,6 @@ package body Synth.Vhdl_Oper is return Synth_Compare (Id_Eq, Boolean_Type); when Iir_Predefined_Integer_Inequality => return Synth_Compare (Id_Ne, Boolean_Type); - when Iir_Predefined_Integer_Minimum => - return Synth_Minmax (Id_Slt); - when Iir_Predefined_Integer_Maximum => - return Synth_Minmax (Id_Sgt); when Iir_Predefined_Physical_Physical_Div => Error_Msg_Synth (+Expr, "non-constant division not supported"); return No_Valtyp; @@ -1670,7 +1657,7 @@ package body Synth.Vhdl_Oper is N := Build_Monadic (Ctxt, Id_Not, N); Set_Location (N, Loc); end if; - return Create_Value_Net (N, Operand.Typ.Vec_El); + return Create_Value_Net (N, Operand.Typ.Arr_El); end Synth_Vec_Reduce_Monadic; begin Operand := Synth_Expression_With_Type (Syn_Inst, Operand_Expr, Oper_Typ); @@ -1788,7 +1775,7 @@ package body Synth.Vhdl_Oper is Expr : Node) return Valtyp is pragma Assert (Left.Typ.Kind = Type_Vector); - Len : constant Uns32 := Left.Typ.Vbound.Len; + Len : constant Uns32 := Left.Typ.Abound.Len; Max : Int32; Rng : Discrete_Range_Type; W : Uns32; @@ -1804,7 +1791,7 @@ package body Synth.Vhdl_Oper is -- The intermediate result is computed using the least number of bits, -- which must represent all positive values in the bounds using a -- signed word (so that -1 is also represented). - Max := Int32'Max (Left.Typ.Vbound.Left, Left.Typ.Vbound.Right); + Max := Int32'Max (Left.Typ.Abound.Left, Left.Typ.Abound.Right); W := Netlists.Utils.Clog2 (Uns32 (Max)) + 1; Rng := (Dir => Dir_To, Is_Signed => True, @@ -1824,17 +1811,17 @@ package body Synth.Vhdl_Oper is if Leftmost then -- Iterate from the right to the left. Pos := I; - if Left.Typ.Vbound.Dir = Dir_To then - V := Int64 (Left.Typ.Vbound.Right) - Int64 (I); + if Left.Typ.Abound.Dir = Dir_To then + V := Int64 (Left.Typ.Abound.Right) - Int64 (I); else - V := Int64 (Left.Typ.Vbound.Right) + Int64 (I); + V := Int64 (Left.Typ.Abound.Right) + Int64 (I); end if; else Pos := Len - I - 1; - if Left.Typ.Vbound.Dir = Dir_To then - V := Int64 (Left.Typ.Vbound.Left) + Int64 (I); + if Left.Typ.Abound.Dir = Dir_To then + V := Int64 (Left.Typ.Abound.Left) + Int64 (I); else - V := Int64 (Left.Typ.Vbound.Left) - Int64 (I); + V := Int64 (Left.Typ.Abound.Left) - Int64 (I); end if; end if; Sel := Build2_Compare (Ctxt, Id_Eq, @@ -1865,6 +1852,23 @@ package body Synth.Vhdl_Oper is (N, Create_Vec_Type_By_Length (Size, Logic_Type)); end Synth_Resize; + function Synth_Minmax (Ctxt : Context_Acc; + Left, Right : Valtyp; + Res_Typ : Type_Acc; + Id : Compare_Module_Id; + Expr : Node) return Valtyp + is + L : constant Net := Get_Net (Ctxt, Left); + R : constant Net := Get_Net (Ctxt, Right); + Sel, N : Net; + begin + Sel := Build2_Compare (Ctxt, Id, L, R); + Set_Location (Sel, Expr); + N := Build_Mux2 (Ctxt, Sel, R, L); + Set_Location (N, Expr); + return Create_Value_Net (N, Res_Typ); + end Synth_Minmax; + function Synth_Dynamic_Predefined_Function_Call (Subprg_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp is @@ -1914,7 +1918,27 @@ package body Synth.Vhdl_Oper is end if; case Def is + when Iir_Predefined_Integer_Minimum => + return Synth_Minmax (Ctxt, L, R, Res_Typ, Id_Slt, Expr); + when Iir_Predefined_Integer_Maximum => + return Synth_Minmax (Ctxt, L, R, Res_Typ, Id_Sgt, Expr); + when Iir_Predefined_Bit_Rising_Edge => + if Hook_Bit_Rising_Edge /= null then + return Create_Value_Memtyp + (Hook_Bit_Rising_Edge.all (L, Res_Typ)); + end if; + raise Internal_Error; + when Iir_Predefined_Bit_Falling_Edge => + if Hook_Bit_Falling_Edge /= null then + return Create_Value_Memtyp + (Hook_Bit_Falling_Edge.all (L, Res_Typ)); + end if; + raise Internal_Error; when Iir_Predefined_Ieee_1164_Rising_Edge => + if Hook_Std_Rising_Edge /= null then + return Create_Value_Memtyp + (Hook_Std_Rising_Edge.all (L, Res_Typ)); + end if; declare Edge : Net; begin @@ -1923,6 +1947,10 @@ package body Synth.Vhdl_Oper is return Create_Value_Net (Edge, Res_Typ); end; when Iir_Predefined_Ieee_1164_Falling_Edge => + if Hook_Std_Falling_Edge /= null then + return Create_Value_Memtyp + (Hook_Std_Falling_Edge.all (L, Res_Typ)); + end if; declare Edge : Net; begin @@ -1930,13 +1958,14 @@ package body Synth.Vhdl_Oper is Set_Location (Edge, Expr); return Create_Value_Net (Edge, Res_Typ); end; - when Iir_Predefined_Ieee_1164_Scalar_Is_X - | Iir_Predefined_Ieee_1164_Vector_Is_X => + when Iir_Predefined_Ieee_1164_Is_X_Log + | Iir_Predefined_Ieee_1164_Is_X_Slv => -- Always false. return Create_Value_Discrete (0, Boolean_Type); when Iir_Predefined_Ieee_1164_To_Bitvector | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv + | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Slv | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn @@ -1957,7 +1986,7 @@ package body Synth.Vhdl_Oper is return Synth_Conv_Vector (False); when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns => declare - B : constant Bound_Type := Get_Array_Bound (R.Typ, 1); + B : constant Bound_Type := Get_Array_Bound (R.Typ); begin return Synth_Resize (Ctxt, L, B.Len, False, Expr); end; @@ -2001,7 +2030,7 @@ package body Synth.Vhdl_Oper is B : Bound_Type; W : Width; begin - B := Get_Array_Bound (R.Typ, 1); + B := Get_Array_Bound (R.Typ); W := B.Len; return Create_Value_Net (Build2_Uresize (Ctxt, Get_Net (Ctxt, L), @@ -2020,7 +2049,7 @@ package body Synth.Vhdl_Oper is (Ctxt, L, Uns32 (Read_Discrete (R)), True, Expr); when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn => declare - B : constant Bound_Type := Get_Array_Bound (R.Typ, 1); + B : constant Bound_Type := Get_Array_Bound (R.Typ); begin return Synth_Resize (Ctxt, L, B.Len, True, Expr); end; |