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-rw-r--r--src/synth/ghdlsynth_gates.h1
-rw-r--r--src/synth/netlists-builders.adb17
-rw-r--r--src/synth/netlists-builders.ads2
-rw-r--r--src/synth/netlists-disp_vhdl.adb2
-rw-r--r--src/synth/netlists-gates.ads3
5 files changed, 25 insertions, 0 deletions
diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h
index 71b29221b..765ad12ce 100644
--- a/src/synth/ghdlsynth_gates.h
+++ b/src/synth/ghdlsynth_gates.h
@@ -58,6 +58,7 @@ enum Module_Id {
Id_Ioutput = 51,
Id_Port = 52,
Id_Inout = 53,
+ Id_Enable = 54,
Id_Dff = 56,
Id_Adff = 57,
Id_Idff = 58,
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index bd8423dac..34ba4a3f1 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -470,6 +470,12 @@ package body Netlists.Builders is
Id_Nop, 1, 1, 0);
Set_Ports_Desc (Ctxt.M_Nop, Inputs2 (0 .. 0), Outputs);
+ Ctxt.M_Enable := New_User_Module
+ (Ctxt.Design,
+ New_Sname_Artificial (Get_Identifier ("enable"), No_Sname),
+ Id_Enable, 1, 1, 0);
+ Set_Ports_Desc (Ctxt.M_Enable, Inputs2 (0 .. 0), Outputs);
+
Ctxt.M_Inout := New_User_Module
(Ctxt.Design, New_Sname_Artificial (Name_Inout, No_Sname),
Id_Inout, 1, 2, 0);
@@ -1398,6 +1404,17 @@ package body Netlists.Builders is
return O;
end Build_Nop;
+ function Build_Enable (Ctxt : Context_Acc) return Net
+ is
+ Inst : Instance;
+ O : Net;
+ begin
+ Inst := New_Internal_Instance (Ctxt, Ctxt.M_Enable);
+ O := Get_Output (Inst, 0);
+ Set_Width (O, 1);
+ return O;
+ end Build_Enable;
+
function Build_Dff (Ctxt : Context_Acc;
Clk : Net;
D : Net) return Net
diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads
index e9b350a74..dc45caf04 100644
--- a/src/synth/netlists-builders.ads
+++ b/src/synth/netlists-builders.ads
@@ -161,6 +161,7 @@ package Netlists.Builders is
function Build_Isignal (Ctxt : Context_Acc; Name : Sname; Init : Net)
return Net;
function Build_Port (Ctxt : Context_Acc; N : Net) return Net;
+ function Build_Enable (Ctxt : Context_Acc) return Net;
function Build_Assert (Ctxt : Context_Acc; Name : Sname; Cond : Net)
return Instance;
@@ -238,6 +239,7 @@ private
M_Isignal : Module;
M_Port : Module;
M_Inout : Module;
+ M_Enable : Module;
M_Dff : Module;
M_Idff : Module;
M_Adff : Module;
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index a4644d4f6..41ef62e36 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -865,6 +865,8 @@ package body Netlists.Disp_Vhdl is
Disp_Template (" \o0 <= \i0; -- (port)" & NL, Inst);
when Id_Nop =>
Disp_Template (" \o0 <= \i0; -- (nop)" & NL, Inst);
+ when Id_Enable =>
+ Disp_Template (" \o0 <= \i0; -- (enable)" & NL, Inst);
when Id_Not =>
Disp_Template (" \o0 <= not \i0;" & NL, Inst);
when Id_Neg =>
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index d45dbc705..f3084105b 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -133,6 +133,9 @@ package Netlists.Gates is
-- 1: direct and only connection to the port
Id_Inout : constant Module_Id := 53;
+ -- Behaves like Id_Signal but for enable wires.
+ Id_Enable : constant Module_Id := 54;
+
-- Note: initial values must be constant nets.
--
-- A simple D flip-flop. The D input is stored on a rising edge of CLK.