diff options
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-aggr.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-decls.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 8 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 68 | ||||
| -rw-r--r-- | src/synth/synth-expr.ads | 2 | ||||
| -rw-r--r-- | src/synth/synth-insts.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-objtypes.adb | 10 | ||||
| -rw-r--r-- | src/synth/synth-objtypes.ads | 6 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 10 | ||||
| -rw-r--r-- | src/synth/synth-static_oper.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 12 | ||||
| -rw-r--r-- | src/synth/synth-values-debug.adb | 6 |
12 files changed, 66 insertions, 66 deletions
diff --git a/src/synth/synth-aggr.adb b/src/synth/synth-aggr.adb index b0f627bd2..ad8b5ea05 100644 --- a/src/synth/synth-aggr.adb +++ b/src/synth/synth-aggr.adb @@ -43,14 +43,14 @@ package body Synth.Aggr is Right : constant Int64 := Int64 (Bounds.Right); begin case Bounds.Dir is - when Iir_To => + when Dir_To => if Index >= Left and then Index <= Right then -- to Off := Uns32 (Index - Left); Err_P := False; return; end if; - when Iir_Downto => + when Dir_Downto => if Index <= Left and then Index >= Right then -- downto Off := Uns32 (Left - Index); diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 003505bc6..81d8a20c9 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -199,7 +199,7 @@ package body Synth.Decls is W : Width; begin W := Uns32 (Clog2 (Uns64 (Nbr_El))); - Rng := (Dir => Iir_To, + Rng := (Dir => Dir_To, Is_Signed => False, Left => 0, Right => Int64 (Nbr_El - 1)); diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 6736343ff..885077e6f 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -187,9 +187,9 @@ package body Synth.Disp_Vhdl is begin for I in 0 .. Bnd.Len - 1 loop case Bnd.Dir is - when Iir_To => + when Dir_To => Idx := Bnd.Left + Int32 (I); - when Iir_Downto => + when Dir_Downto => Idx := Bnd.Left - Int32 (I); end case; Disp_In_Converter @@ -343,9 +343,9 @@ package body Synth.Disp_Vhdl is begin for I in 0 .. Bnd.Len - 1 loop case Bnd.Dir is - when Iir_To => + when Dir_To => Idx := Bnd.Left + Int32 (I); - when Iir_Downto => + when Dir_Downto => Idx := Bnd.Left - Int32 (I); end case; Disp_Out_Converter diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 54f8d9916..87f3c4ac1 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -418,7 +418,7 @@ package body Synth.Expr is end Concat_Array; function Synth_Discrete_Range_Expression - (L : Int64; R : Int64; Dir : Iir_Direction) return Discrete_Range_Type is + (L : Int64; R : Int64; Dir : Direction_Type) return Discrete_Range_Type is begin return (Dir => Dir, Left => L, @@ -585,10 +585,10 @@ package body Synth.Expr is B := Synth_Array_Attribute (Syn_Inst, Bound); -- Reverse case B.Dir is - when Iir_To => - B.Dir := Iir_Downto; - when Iir_Downto => - B.Dir := Iir_To; + when Dir_To => + B.Dir := Dir_Downto; + when Dir_Downto => + B.Dir := Dir_To; end case; T := B.Right; B.Right := B.Left; @@ -924,7 +924,7 @@ package body Synth.Expr is Res : Valtyp; begin Bnd := Create_Bound_Array (1); - Bnd.D (1) := (Dir => Iir_To, Left => 1, Right => Int32 (Len), + Bnd.D (1) := (Dir => Dir_To, Left => 1, Right => Int32 (Len), Len => Width (Len)); Typ := Create_Array_Type (Bnd, Styp.Uarr_El); @@ -1011,9 +1011,9 @@ package body Synth.Expr is function In_Bounds (Bnd : Bound_Type; V : Int32) return Boolean is begin case Bnd.Dir is - when Iir_To => + when Dir_To => return V >= Bnd.Left and then V <= Bnd.Right; - when Iir_Downto => + when Dir_Downto => return V <= Bnd.Left and then V >= Bnd.Right; end case; end In_Bounds; @@ -1034,10 +1034,10 @@ package body Synth.Expr is -- The offset is from the LSB (bit 0). Bit 0 is the rightmost one. case Bnd.Dir is - when Iir_To => + when Dir_To => Res.Net_Off := Uns32 (Bnd.Right - Int32 (Idx)); Res.Mem_Off := Size_Type (Int32 (Idx) - Bnd.Left); - when Iir_Downto => + when Dir_Downto => Res.Net_Off := Uns32 (Int32 (Idx) - Bnd.Right); Res.Mem_Off := Size_Type (Bnd.Left - Int32 (Idx)); end case; @@ -1056,7 +1056,7 @@ package body Synth.Expr is Wbounds := Clog2 (Bnd.Len); Idx2 := Synth_Resize (Idx_Val, Wbounds, Loc); - if Bnd.Right = 0 and then Bnd.Dir = Iir_Downto then + if Bnd.Right = 0 and then Bnd.Dir = Dir_Downto then -- Simple case without adjustments. return Idx2; end if; @@ -1066,10 +1066,10 @@ package body Synth.Expr is Set_Location (Right, Loc); case Bnd.Dir is - when Iir_To => + when Dir_To => -- L <= I <= R --> off = R - I Off := Build_Dyadic (Build_Context, Id_Sub, Right, Idx2); - when Iir_Downto => + when Dir_Downto => -- L >= I >= R --> off = I - R Off := Build_Dyadic (Build_Context, Id_Sub, Idx2, Right); end case; @@ -1321,10 +1321,10 @@ package body Synth.Expr is end if; case Pfx_Bnd.Dir is - when Iir_To => + when Dir_To => Off := Uns32 (L_Add - Pfx_Bnd.Left); Width := Uns32 (R_Add - L_Add + 1); - when Iir_Downto => + when Dir_Downto => Off := Uns32 (R_Add - Pfx_Bnd.Right); Width := Uns32 (L_Add - R_Add + 1); end case; @@ -1335,7 +1335,7 @@ package body Synth.Expr is Name : Node; Pfx_Bnd : Bound_Type; L, R : Int64; - Dir : Iir_Direction; + Dir : Direction_Type; El_Typ : Type_Acc; Res_Bnd : out Bound_Type; Off : out Value_Offsets) @@ -1346,19 +1346,19 @@ package body Synth.Expr is if Pfx_Bnd.Dir /= Dir then Error_Msg_Synth (+Name, "direction mismatch in slice"); Off := (0, 0); - if Dir = Iir_To then - Res_Bnd := (Dir => Iir_To, Left => 1, Right => 0, Len => 0); + if Dir = Dir_To then + Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0); else - Res_Bnd := (Dir => Iir_Downto, Left => 0, Right => 1, Len => 0); + Res_Bnd := (Dir => Dir_Downto, Left => 0, Right => 1, Len => 0); end if; return; end if; -- Might be a null slice. case Pfx_Bnd.Dir is - when Iir_To => + when Dir_To => Is_Null := L > R; - when Iir_Downto => + when Dir_Downto => Is_Null := L < R; end case; if Is_Null then @@ -1375,11 +1375,11 @@ package body Synth.Expr is end if; case Pfx_Bnd.Dir is - when Iir_To => + when Dir_To => Len := Uns32 (R - L + 1); Off.Net_Off := Uns32 (Pfx_Bnd.Right - Int32 (R)) * El_Typ.W; Off.Mem_Off := Size_Type (Int32 (L) - Pfx_Bnd.Left) * El_Typ.Sz; - when Iir_Downto => + when Dir_Downto => Len := Uns32 (L - R + 1); Off.Net_Off := Uns32 (Int32 (R) - Pfx_Bnd.Right) * El_Typ.W; Off.Mem_Off := Size_Type (Pfx_Bnd.Left - Int32 (L)) * El_Typ.Sz; @@ -1401,7 +1401,7 @@ package body Synth.Expr is is Expr : constant Node := Get_Suffix (Name); Left, Right : Valtyp; - Dir : Iir_Direction; + Dir : Direction_Type; Step : Uns32; Max : Uns32; Inp_W : Width; @@ -1445,10 +1445,10 @@ package body Synth.Expr is Error_Msg_Synth (+Name, "direction mismatch in slice"); Inp := No_Net; Off := (0, 0); - if Dir = Iir_To then - Res_Bnd := (Dir => Iir_To, Left => 1, Right => 0, Len => 0); + if Dir = Dir_To then + Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0); else - Res_Bnd := (Dir => Iir_Downto, Left => 0, Right => 1, Len => 0); + Res_Bnd := (Dir => Dir_Downto, Left => 0, Right => 1, Len => 0); end if; return; end if; @@ -1705,7 +1705,7 @@ package body Synth.Expr is -- Return the left bound if the direction of the range is LEFT_DIR. function Synth_Low_High_Type_Attribute - (Syn_Inst : Synth_Instance_Acc; Expr : Node; Left_Dir : Iir_Direction) + (Syn_Inst : Synth_Instance_Acc; Expr : Node; Left_Dir : Direction_Type) return Valtyp is Typ : Type_Acc; @@ -1965,9 +1965,9 @@ package body Synth.Expr is begin B := Synth_Array_Attribute (Syn_Inst, Expr); case B.Dir is - when Iir_To => + when Dir_To => V := B.Right; - when Iir_Downto => + when Dir_Downto => V := B.Left; end case; return Create_Value_Discrete (Int64 (V), Expr_Type); @@ -1979,9 +1979,9 @@ package body Synth.Expr is begin B := Synth_Array_Attribute (Syn_Inst, Expr); case B.Dir is - when Iir_To => + when Dir_To => V := B.Left; - when Iir_Downto => + when Dir_Downto => V := B.Right; end case; return Create_Value_Discrete (Int64 (V), Expr_Type); @@ -2007,9 +2007,9 @@ package body Synth.Expr is return Synth_Subtype_Conversion (V, Dtype, False, Expr); end; when Iir_Kind_Low_Type_Attribute => - return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Iir_To); + return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_To); when Iir_Kind_High_Type_Attribute => - return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Iir_Downto); + return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_Downto); when Iir_Kind_Value_Attribute => return Synth_Value_Attribute (Syn_Inst, Expr); when Iir_Kind_Image_Attribute => diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index d03f2f92c..ef0499dc1 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -90,7 +90,7 @@ package Synth.Expr is Dim : Dim_Type) return Bound_Type; function Synth_Discrete_Range_Expression - (L : Int64; R : Int64; Dir : Iir_Direction) return Discrete_Range_Type; + (L : Int64; R : Int64; Dir : Direction_Type) return Discrete_Range_Type; function Synth_Discrete_Range_Expression (Syn_Inst : Synth_Instance_Acc; Rng : Node) return Discrete_Range_Type; function Synth_Float_Range_Expression diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index e4c5cf608..bdc9f040a 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -171,7 +171,7 @@ package body Synth.Insts is procedure Hash_Bound (C : in out GNAT.SHA1.Context; B : Bound_Type) is begin - Hash_Uns64 (C, Iir_Direction'Pos (B.Dir)); + Hash_Uns64 (C, Direction_Type'Pos (B.Dir)); Hash_Uns64 (C, To_Uns64 (Int64 (B.Left))); Hash_Uns64 (C, To_Uns64 (Int64 (B.Right))); end Hash_Bound; diff --git a/src/synth/synth-objtypes.adb b/src/synth/synth-objtypes.adb index cd199d724..8c9867a28 100644 --- a/src/synth/synth-objtypes.adb +++ b/src/synth/synth-objtypes.adb @@ -124,10 +124,10 @@ package body Synth.Objtypes is W : Width; begin case Rng.Dir is - when Iir_To => + when Dir_To => Lo := Rng.Left; Hi := Rng.Right; - when Iir_Downto => + when Dir_Downto => Lo := Rng.Right; Hi := Rng.Left; end case; @@ -250,7 +250,7 @@ package body Synth.Objtypes is function Create_Vec_Type_By_Length (Len : Width; El : Type_Acc) return Type_Acc is begin - return Create_Vector_Type ((Dir => Iir_Downto, + return Create_Vector_Type ((Dir => Dir_Downto, Left => Int32 (Len) - 1, Right => 0, Len => Len), @@ -370,9 +370,9 @@ package body Synth.Objtypes is Len : Int64; begin case Rng.Dir is - when Iir_To => + when Dir_To => Len := Rng.Right - Rng.Left + 1; - when Iir_Downto => + when Dir_Downto => Len := Rng.Left - Rng.Right + 1; end case; if Len < 0 then diff --git a/src/synth/synth-objtypes.ads b/src/synth/synth-objtypes.ads index a332536d1..c79a473c4 100644 --- a/src/synth/synth-objtypes.ads +++ b/src/synth/synth-objtypes.ads @@ -30,7 +30,7 @@ with Vhdl.Nodes; use Vhdl.Nodes; package Synth.Objtypes is type Discrete_Range_Type is record -- An integer range. - Dir : Iir_Direction; + Dir : Direction_Type; -- Netlist representation: signed or unsigned, width of vector. Is_Signed : Boolean; @@ -43,13 +43,13 @@ package Synth.Objtypes is function Discrete_Range_Width (Rng : Discrete_Range_Type) return Width; type Float_Range_Type is record - Dir : Iir_Direction; + Dir : Direction_Type; Left : Fp64; Right : Fp64; end record; type Bound_Type is record - Dir : Iir_Direction; + Dir : Direction_Type; Left : Int32; Right : Int32; Len : Width; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 758ca6b06..2ee88c328 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -128,7 +128,7 @@ package body Synth.Oper is begin Res := Prev.Typ; - if Res.Vbound.Dir = Iir_Downto + if Res.Vbound.Dir = Dir_Downto and then Res.Vbound.Right = 0 then -- Normalized range @@ -156,16 +156,16 @@ package body Synth.Oper is -- Special case. Res.Right := Res.Left; case Index_Bounds.Dir is - when Iir_To => + when Dir_To => Res.Left := Res.Right + 1; - when Iir_Downto => + when Dir_Downto => Res.Left := Res.Right - 1; end case; else case Index_Bounds.Dir is - when Iir_To => + when Dir_To => Res.Right := Res.Left + Int32 (Len - 1); - when Iir_Downto => + when Dir_Downto => Res.Right := Res.Left - Int32 (Len - 1); end case; end if; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 64316280d..e4249740f 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -226,7 +226,7 @@ package body Synth.Static_Oper is function Create_Res_Bound (Prev : Type_Acc) return Type_Acc is begin - if Prev.Vbound.Dir = Iir_Downto + if Prev.Vbound.Dir = Dir_Downto and then Prev.Vbound.Right = 0 then -- Normalized range diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index b41a9ba69..efece924c 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1119,9 +1119,9 @@ package body Synth.Stmts is Synth_Discrete_Range (C.Inst, Get_Choice_Range (Choice), Bnd); case Bnd.Dir is - when Iir_To => + when Dir_To => Is_In := Sel >= Bnd.Left and Sel <= Bnd.Right; - when Iir_Downto => + when Dir_Downto => Is_In := Sel <= Bnd.Left and Sel >= Bnd.Right; end case; if Is_In then @@ -1970,9 +1970,9 @@ package body Synth.Stmts is function In_Range (Rng : Discrete_Range_Type; V : Int64) return Boolean is begin case Rng.Dir is - when Iir_To => + when Dir_To => return V >= Rng.Left and then V <= Rng.Right; - when Iir_Downto => + when Dir_Downto => return V <= Rng.Left and then V >= Rng.Right; end case; end In_Range; @@ -1983,9 +1983,9 @@ package body Synth.Stmts is begin T := Read_Discrete (V); case Rng.Dir is - when Iir_To => + when Dir_To => T := T + 1; - when Iir_Downto => + when Dir_Downto => T := T - 1; end case; Write_Discrete (V, T); diff --git a/src/synth/synth-values-debug.adb b/src/synth/synth-values-debug.adb index e28b3ab5e..493c30e7e 100644 --- a/src/synth/synth-values-debug.adb +++ b/src/synth/synth-values-debug.adb @@ -23,12 +23,12 @@ with Utils_IO; use Utils_IO; with Vhdl.Nodes; use Vhdl.Nodes; package body Synth.Values.Debug is - procedure Put_Dir (Dir : Iir_Direction) is + procedure Put_Dir (Dir : Direction_Type) is begin case Dir is - when Iir_To => + when Dir_To => Put ("to"); - when Iir_Downto => + when Dir_Downto => Put ("downto"); end case; end Put_Dir; |